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Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase
The TPS59650EVM-753 evaluation module (EVM) is a complete solution for Intel™ IMVP7 Serial
VID(SVID) Power System from a 9V-20V input bus. This EVM uses the TPS59650 for IMVP7 - 3-Phase
CPU and 2-Phase GPU Vcore controller, the TPS51219 for 1.05VCCIO, TPS51916 for DDR3L/DDR4
Memory rail (1.2VDDQ, 0.6VTT and 0.6VTTREF) and also uses the (CSD87350Q5D) a 5mm x 6mm TI's
power block MOSFETs that uses Powerstack™ technology with high-side and low-side MOSFETs for high
power density and superior thermal performance.
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TPS59650EVM-753 Power System Block Diagram
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Powerstack is a trademark of Texas Instruments.
Intel is a trademark of Intel.
All other trademarks are the property of their respective owners.
SLUU896 - March 2012
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CPU/2-Phase GPU SVID Power System
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Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU
Copyright © 2012, Texas Instruments Incorporated
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List of Figures
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User's Guide
SLUU896 - March 2012
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SVID Power System
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Summary of Contents for Texas Instruments TPS59650EVM-753
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Page 1: Table Of Contents
Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System The TPS59650EVM-753 evaluation module (EVM) is a complete solution for Intel™ IMVP7 Serial VID(SVID) Power System from a 9V-20V input bus. This EVM uses the TPS59650 for IMVP7 - 3-Phase CPU and 2-Phase GPU Vcore controller, the TPS51219 for 1.05VCCIO, TPS51916 for DDR3L/DDR4... - Page 2 ....................GPU2 Enable Turn on ....................GPU2 Enable Turn off ..................GPU2 Switching Node and Ripple Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
- Page 3 TPS59650EVM-753 Internal Layer 2 .................. TPS59650EVM-753 Internal Layer 3 .................. TPS59650EVM-753 Internal Layer 4 ................... TPS59650EVM-753 Internal Layer 5 SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
- Page 4 VCCIO Output Voltage Selection ..............On Board Dynamic Load Enable/Disable selection .................... EVM Major Components List Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
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Page 5: Description
Description The TPS59650EVM-753 is designed to use a 9V-20V Input bus to produce 6 regulated outputs for IMVP7 SVID CPU/GPU Power System. The TPS59650EVM-753 is specially designed to demonstrate the TPS59650 full IMVP7 mobile feature while providing GUI communication programing and a number of test points to evaluate the static and dynamic performance of TPS59650. -
Page 6: Tps59650Evm-753 Power System Block Diagram
VCCIO: 0A-10A GUI communication TMS320F2808PZS USB Cable TUSB3410RHB Host Computer Figure 1. TPS59650EVM-753 Power System Block Diagram Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 7: Electrical Performance Specifications
SVID: Address:01 GPU, Payload: 1.23V 1.23 Jumpers set to default locations, see section 6 of this user’s guide SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 8: Test Setup
USB Cable The USB Cable: Standard USB_A to USB_B 5 Pin Mini-B cable. See Figure 3 Figure 3. USB Cable Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 9: Recommended Wire Gauge
TPS59650 USB driver and SVID GUI Installation 1. Copy the both files: setup.exe and setup.msi to the host computer. 2. Run this setup.exe. 3. Following installation Instructions, this will install the driver and the Texas Instruments SVID GUI. 4. It will add the below icon 4.1.4... -
Page 10: Usb Cable Connections
TP24 (GND) to measure 12VBAT voltage as shown in Figure 4. Connect a current meter A1 between 12VBAT DC source and J21 to measure the 12VBAT input current. Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback... -
Page 11: Output Connections
(11-12 pin shorted) 30.1k 350 kHz (13-14 pin shorted) 24.3k 300 kHz Right(15-16 pin shorted) 20.0k 250 kHz SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 12: Gpu Frequency Selection
Push S2(lower) to “ON” position Enable 10A on board dynamic load at VCCIO Push S2(lower) to “OFF” position Disable 10A on board dynamic load at VCCIO Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID SLUU896 – March 2012 Power System Submit Documentation Feedback... -
Page 13: Vddq, 0.6V Vtt And 0.6V Vttref Configuration
Jumper shorts on Pin1 and Pin2 VCCIO: 1.05V Jumper shorts on Pin2 and Pin3 VCCIO: 1.00V SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 14: Test Procedure
18. Decrease LOAD to 0A and disconnect the LOAD from terminal J1, J2, J3 19. Disconnect V3 from J7. 20. Disconnect scope probe from TP30 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright ©... -
Page 15: Tps59650Evm-753 Cpu Gui Set Up Window
Test Procedure www.ti.com Figure 5. TPS59650EVM-753 CPU GUI set up Window 6.1.2 1. Connect the LOAD to GPU terminal J4, J5 and V3 at J9. Ensure correct polarity. 2. Add scope probe on the TP46 for GPU Vcore_G ripple measurement 3. -
Page 16: Tps59650Evm-753 Gpu Gui Set Up Window
Test Procedure www.ti.com Figure 6. TPS59650EVM-753 GPU GUI set up Window 6. Measure V3: GPU Vcore_G at J9 and A1: 12VBAT input current 7. Vary GPU LOAD from 0Adc to 50Adc, GPU Vcore must remain in load line 8. Vary 12VBAT from 9V to 20V GPU Vcore must remain in line regulation 9. -
Page 17: Equipment Shutdown
1. Shut down Load 2. Shut down 12VBAT and 5Vin 3. Shut down oscilloscope 4. Shut down host computer SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 18: Performance Data And Typical Characteristic Curves
Performance Data and Typical Characteristic Curves Figure 7 through Figure 91 present typical performance curves for TPS59650EVM-753. Jumpers set to default locations, see section 6 of this user’s guide. CPU 3-Phase Operation V = 12 V V = 9 V V = 9 V 1.05... -
Page 19: Cpu3 Switching Node(Ripple)
CH3: 1.05V core CH4: VDIO CH4: VDIO Figure 13. CPU3 Dynamic VID:SetVID-Fast/Fast Figure 14. CPU3 Dynamic VID:SetVID-Decay/Fast SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 20: Cpu3 Output Load Insertion With Osr/Usr Middle Level
Figure 17. CPU3 Bode Plot at 12Vin, 1.05V/60A Test condition: CPU3 12Vin, 1.05V/60A no airflow Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 21: Cpu 2-Phase Operation
I - Output Current - A I - Output Current - A Figure 20. CPU2 Efficiency Figure 21. CPU2 Load regulation SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 22: Cpu2 Enable Turn On
CH3: 1.05Vcore CH4: VDIO CH4: 1.05Vcore Figure 24. CPU2 Switching Node(Ripple) Figure 25. CPU2 Dynamic VID: SetVID-Slow/Slow Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 23: Cpu2 Dynamic Vid:setvid-Fast/Fast
Figure 28. CPU2 Output Load Insertion with OSR/USR Figure 29. CPU2 Output Load Release with OSR/USR middle level middle level SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 24: Cpu2 Bode Plot At 12Vin, 1.05V/55A
Figure 30. CPU2 Bode Plot at 12Vin, 1.05V/55A Test condition: CPU2 12Vin, 1.05V/55A no airflow Figure 31. CPU2 MOSFET Figure 32. CPU2 IC Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback... -
Page 25: Cpu1-Phase Operation
CH4: CPGOOD CH4: CPGOOD Figure 35. CPU1 Enable Turn on Figure 36. CPU1 Enable Turn off SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 26: Cpu1 Switching Node
CH3: 1.05Vcore CH4: VDIO CH4: VDIO Figure 39. CPU1 Dynamic VID:SetVID-Slow/Slow Figure 40. CPU1 Dynamic VID:SetVID-Fast/Fast Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 27: Cpu1 Dynamic Vid:setvid-Decay/Fast
CH1: DYN_C CH2: CSW1 CH3: 1.05Vcore Figure 43. CPU1 Output Load Release with OSR/USR middle level SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 28: Cpu1 Bode Plot At 12Vin, 1.05V/33A
Figure 44. CPU1 Bode Plot at 12Vin, 1.05V/33A Test condition: CPU1 12Vin, 1.05V/33A no airflow Figure 45. CPU1 MOSFET Figure 46. CPU1 IC Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback... -
Page 29: Gpu 2 Phase Operation
CH4: GPGOOD CH4: GPGOOD Figure 49. GPU2 Enable Turn on Figure 50. GPU2 Enable Turn off SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 30: Gpu2 Switching Node And Ripple
CH3: 1.23Vcore_G CH4: VDIO CH4: VDIO Figure 53. GPU2 Dynamic VID:SetVID-Fast/Fast Figure 54. GPU2 Dynamic VID:SetVID-Decay/Fast Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 31: Gpu2 Bode Plot At 12Vin, 1.23V/50A
Figure 55. GPU2 Output Load Insertion with OSR/USR Figure 56. GPU2 Output Load Release with OSR/USR Figure 57. GPU2 Bode Plot at 12Vin, 1.23V/50A Test condition: GPU2 12Vin, 1.23V/50A no airflow SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 32: Gpu 1 Phase Operation
I - Output Current - A I - Output Current - A Figure 60. GPU1 Efficiency Figure 61. GPU1 Load regulation Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 33: Gpu1 Enable Turn On
CH1: GSW1 CH3: 1.23Vcore Ripple Figure 64. GPU1 Switching Node Figure 65. GPU1 Switching Node and Ripple SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 34: Gpu1 Dynamic Vid:setvid-Slow/Slow
CH4: VDIO CH3: 1.23Vcore Figure 68. GPU1 Dynamic VID:SetVID-Decay/Fast Figure 69. GPU1 Output Load Insertion with OSR/USR Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 35: Gpu1 Output Load Release With Osr/Usr Off
Figure 70. GPU1 Output Load Release with OSR/USR OFF Figure 71. GPU1 Bode Plot at 12Vin, 1.23V/33A Test condition: GPU1 12Vin, 1.23V/33A no airflow SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 36: Vccio
I - Output Current - A I - Output Current - A Figure 74. 1.05V Efficiency Figure 75. 1.05V Load regulation Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 37: V Switching Node
VCCIO Output Ripple CH1: SW CH1: VCCIO Output Ripple Figure 78. 1.05V Switching Node Figure 79. 1.05V Ripple SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 38: Tps51219 Thermal
Figure 80. 1.05V Transient DCM TO CCM Figure 81. 1.05V Transient CCM to DCM Test condition: 12Vin, 1.05V/10A no airflow Figure 82. TPS51219 Thermal Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback... -
Page 39: Vddq
CH4: VDDQ_PG CH4: VDDQ_PG Figure 85. 1.2V Enable Turn on Figure 86. 1.2V Enable Turn off SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... - Page 40 CH4: VDDQ Output current Figure 89. 1.2V Transient DCM TO CCM Figure 90. 1.2V Transient CCM to DCM Test condition: 12Vin, 1.2V/7.5A no airflow Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback...
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Page 41: Tps51916 Thermal
Performance Data and Typical Characteristic Curves www.ti.com Figure 91. TPS51916 Thermal SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 42: Evm Assembly Drawings And Pcb Layout
101) show the design of the TPS59650EVM-753 printed circuit board. The EVM has been designed using 8 Layers circuit board with 1oz copper on outside layers. Figure 92. TPS59650EVM-753 Top Layer Assembly Drawing (Top view) Figure 93. TPS59650EVM-753 Bottom Assembly Drawing (Bottom view) Using the TPS59650EVM-753 Intel™... -
Page 43: Tps59650Evm-753 Top Copper
EVM Assembly Drawings and PCB Layout www.ti.com Figure 94. TPS59650EVM-753 Top Copper Figure 95. TPS59650EVM-753 Bottom Copper SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 44: Tps59650Evm-753 Internal Layer
EVM Assembly Drawings and PCB Layout www.ti.com Figure 96. TPS59650EVM-753 Internal Layer 2 Figure 97. TPS59650EVM-753 Internal Layer 3 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 45: Tps59650Evm-753 Internal Layer
EVM Assembly Drawings and PCB Layout www.ti.com Figure 98. TPS59650EVM-753 Internal Layer 4 Figure 99. TPS59650EVM-753 Internal Layer 5 SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 46: Using The Tps59650Evm-753 Intel™ Imvp-7 3-Phase Cpu/2-Phase Gpu Sluu896 - March 2012
EVM Assembly Drawings and PCB Layout www.ti.com Figure 100. TPS59650EVM-753 Internal Layer 6 Figure 101. TPS59650EVM-753 Internal Layer 7 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... -
Page 47: Bill Of Materials
D1, D2, D3, D9, D10, D12, Diode, LED, Green Clear, 20mcd, 0.079x0.049 Lite On LTST-C170GKT D13, D14 SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... - Page 48 R198, R199, R203, R204, Resistor, Chip, 1M, 1/16W, 1%, 0402 R206, R207 Resistor, Chip, 130, 1/16W, 1%, 0402 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
- Page 49 IC, Dual low dropout regulator, 500mA and 250mA outputs, PWP20 TPS70102PWP IC, 150mA, low Iq, wide bandwidth, LDO, SC70 TPS71712DCK SLUU896 – March 2012 Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated...
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Page 50: Schematics
Crystal, controlled oscillators, 0.150”x0.528” ABRACON ABLS-20.000MHZ-B2-T Crystal, controlled oscillators, 0.150”x0.528” ABRACON ABLS-12.000MHZ-B2-T Socket, CPU Molex rPGA989 Schematics Using the TPS59650EVM-753 Intel™ IMVP-7 3-Phase CPU/2-Phase GPU SLUU896 – March 2012 SVID Power System Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated... - Page 65 Any exceptions to this are strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory authorities, which is responsibility of user including its acceptable authorization.
- Page 66 FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
- Page 67 Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjukku-ku, Tokyo, Japan http://www.tij.co.jp...
- Page 68 FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate Assurance and Indemnity Agreement. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated...
- Page 69 Any exceptions to this are strictly prohibited and unauthorized by Texas Instruments unless user has obtained appropriate experimental/development licenses from local regulatory authorities, which is responsibility of user including its acceptable authorization.
- Page 70 FCC Interference Statement for Class B EVM devices This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
- Page 71 Also, please do not transfer this product, unless you give the same notice above to the transferee. Please note that if you could not follow the instructions above, you will be subject to penalties of Radio Law of Japan. Texas Instruments Japan Limited (address) 24-1, Nishi-Shinjuku 6 chome, Shinjuku-ku, Tokyo, Japan http://www.tij.co.jp...
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Page 72: Copyright © 2012, Texas Instruments Incorporated
FDA Class III or similar classification, then you must specifically notify TI of such intent and enter into a separate Assurance and Indemnity Agreement. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2012, Texas Instruments Incorporated... - Page 73 IMPORTANT NOTICE FOR TI REFERENCE DESIGNS Texas Instruments Incorporated ("TI") reference designs are solely intended to assist designers (“Buyers”) who are developing systems that incorporate TI semiconductor products (also referred to herein as “components”). Buyer understands and agrees that Buyer remains responsible for using its independent analysis, evaluation and judgment in designing Buyer’s systems and products.
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