JVC NX-MD1R Service Manual page 57

MIIL1644SA-50T (IC390) : DRAM
1. Terminal layout
VDD 1
D0 2
D1 3
WE 4
RAS 5
A11 6
A10 8
A0 9
A1 10
A2 11
A3 12
VDD 13
3. Block diagram
WE
CAS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
(A11)
RAS
2. Pin function
26 VSS
25 D3
24 D2
23 CAS
22 OE
21 A9
19 A8
18 A7
17 A6
16 A5
15 A4
14 VSS
Data input
CAS clock
generator
(11/10)
Colum pre
decoder(11/10)
Reflesh
controller
Reflesh
counter
Low pre decoder
(11/12)
(11/12)
RAS clock
generator
X16 parallel
test
Pin No. Symbol
VDD
1.13
DO~D3
2.3.24.25
4 WE
RAS
5
AO~A11
6.8~12.
15~19.21
AO~A10
8~12.
15~19.21
VSS
14.26
OE
22
CAS
23
DO D1 D2 D3
4
4
Data output
buffer
buffer
D0~3 D0~3
Colum decoder
Sense amp
I/O gate
Memory arry
Low
4,194,304 x 4
decoder
Sub straight generator
NX-MD1R/NX-MD1
Function
Power supply(3.3V)
Data I/O
Write enable
load adress strobe
Adress input
(4K Refresh Product)
Adress input
(2K Refresh Product)
Ground
Output enable
Colum adress strobe
OE
VDD
VSS
1-57