Motorola MTH500 Service Manual page 126

SCHEMATIC DIAGRAMS - MTH500 REDCAP 2 Block (Sheet 1 of 2)
MTH500 REDCAP 2 Block (Sheet 1 of 2)
SIM_CARD
SIM_POWER O
SIM_RESET O
SIM_DATA
I/O
SIM_CLOCK O
GCAP3_RX O
GCAP3_TX
I
GCAP3_DCLK
I
GCAP3
GCAP3_FSYNC I
SPIA_MISO
I
SPIA_MOSI O
SPIA_CLK O
SPIA
SPIA_CS0_WPIC
O
SPIA_CS2_ODCT O
SYNT_CS_ O
SPIB_MISO
I
SPIB_MOSI O
SPIB_CLK O
SPIB
SPIB_CS1_DISPLAY
O
SPIB_CS2_GCAP3
O
HST_DATA(0:15)
V3_2.775V_FLTR
V3_2.775V_FLTR
4
A2
OE
1 EN_OE
G5
C425 C401 EN_WE
3
10n 100.n
EB1 A1
LB
2
EB0 B2
6 UB
B5
CS2_
CS2#-SRAM
CS1
A6
U402
CS2
K6F8016U6A
1 A3 B6 0
A0 DO
2 A4 C5 1
A1 D1
A5 C6 2
3
A2 D2
4 B3 D5 3
A3 D3
5 B4 E5 4
A4 D4
6 C3 F5 5
A5 D5
7 C4 F6 6
A6 D6
D4 G6 7
8
A7 D7
9 H2 B1 8
A8 D8
10 H3 C1 9
A9 D9
11 H4 C2 10
A10 D10
12 H5 D2 11
A11 D11
G3 E2 12
13
A12 D12
14 G4 F2 13
A13 D13
15 F3 F1 14
A14 D14
16 F4 G1 15
A15 D15
17 E4
A16
18 D3 G2
A17 NC1
19 H1 H6
A18 NC2
INT0 - PTT
PTT
I
INT1 - GCAPIII INT
GCAP3_INT
I
INTERRUPT
INT4 - Option_Select_1
OPT_SEL_1 I
INT5 - Option_Select_2
OPT_SEL_2 I
INPUTS
RESET_2.5V-2.7V Low_Voltage_Dector (Connect to GCAP3 RESETB Pin)
LV_DETECT I
MOD I
6 - 24
1
1 MCU_DE
TP401
2
3 R401 0 RESET_OUT
5
DSP_STD goes to GCAPIII_RX D16
STDA
AUDIO
DSP_SRD goes to GCAPIII_TX D13
SRDA
GCAP3 Audio Serial Port Clock C15
SCKA
B16
TP409 SC0A
A16
TP410
SC1A
A15 CODEC
GCAP3 Audio Serial Port Frame Sync
SC2A
B9
MISOA
C9
MOSIA
A9
SPI_CKA
WPIC D9
SPICS0A
E11
SPICS1A
QSPI-A
ODCT E10
SPICS2A
E9
SYNT
SPICS3A
F7
SWB+_EN
SPICS4A
C11
MISOB
D12
MOSIB
D11
SPI_CKB
D10
SPICS0B
C10
SPICS1B QSPI-B
B10
SPICS2B
A10
SPICS3B
E12
VIBR_EN
SPICS4B
HST_Addr(0:21) 0 J2
ADDR0
1 J1
ADDR1
V3_2.775V_FLTR 2 J4
ADDR2
3 L5
ADDR3
4 K6
ADDR4
5 J6
ADDR5
C412 100.n 6 H6
ADDR6
7 G6
ADDR7
8 H5
ADDR8
C426 10n 9 G5
ADDR9
10 F5
TP413
ADDR10
11 H4
ADDR11
U403
12 H1
ADDR12
13 H2
28F320C3
ADDR13
5 D7 14 H3
EN_CE ADDR14
4 F8 15 E5
EN_OE ADDR15
3 B3 16 G3
EN_WE ADDR16
B4 17 G4
EN_RP ADDR17
18 F4
A5
EN_WP ADDR18
19 F1
ADDR19
1 D8 E7 0 20 F2
A0 DQ0
ADDR20
2 C8 F7 1 21 F3
A1 DQ1 ADDR21
FLASH 2
3 B8 D5 0 T1
A2 DQ2 D0
C7 2 Meg x16 E5 3 1 T2
4
EIM
A3 DQ3 D1
5 A8 F4 4 2 T3
A4 DQ4 D2
6 B7 D3 5 3 R3
A5 DQ5 D3
7 C6 E3 6 4 P3
A6 DQ6 D4
7
8 A7 F2 5 T4
A7 DQ7 D5
A3 D6 8 6 R4
9
A8 DQ8 D6
10 C3 E6 9 7 P4
A9 DQ9 D7
11 B2 F6 10 8 P5
A10 DQ10
D8
12 A2 D4 11 9 N5
A11 DQ11 D9
12
13 C2 E4 10 P6
A12 DQ12 D10
A1 F3 13 11 R6
14
A13 DQ13 D11
15 B1 D2 14 12 T6
A14 DQ14 D12
16 C1 E2 15 13 N6
A15 DQ15 D13
17 D1 14 N7
A16 D14
18 B6 C4 15 P7
A17 NC1 D15
B5
19
A18
20 A6
A19
21 C5
A20
MEM_CNTL(6:1)
RESET_OUT
INT0 - PTT
INT1 - GCAPIII INT
INT4 - Option_Select_1
INT5 - Option_Select_2
MOD
SIM_BUS(5:1)
JTAG AND TEST SMART CARD
BASEBAND
CODEC PORT
LAYER1 TIMER
U401
30C40
REDCAP2
17x17mm BGA
CLOCK AND PLL
RTSA_IC2A_RESET_IN
UART-A
UART-B
ROW7_RI_SCKA_TCK
ROW6_DCD_SC2A_DSP_DE
KEYPAD
EMU AND DEBUG INTERRUPTS
RESET_OUT
R405
22.K
1
TP402
A14 WPIC Serial Port STD Pin 83
STDB O WPIC_STD
B14 WPIC Serial Port SRD Pin 77
SRDB I WPIC_SRD
C13 WPIC Serial Port CLK Pin 25
SCKB I WPIC_TXCLK
B13
SC0B
A13
WPIC
SC1B WPIC Serial Port Frame Sync Pin 24
C14
WPIC_FSYNC
SC2B I
A12
SCKB2
B12
SRDB2
A5
TOUT0 O LO_Driver_En
C5
TOUT1 O LO_Mixer_En
D5
TOUT2 O WPIC_TXE
C6
TOUT3 O PA_Bias
B6
TOUT4 O GCAP3_AD_TRIGGER
A6
TOUT5 O ANT_EN
D6
TOUT6
D7
TOUT7
C7
TOUT8 O TETRA_MAIN_VCO_ON
B7
TOUT9 O VA_EN
B8
TOUT10
A8
TOUT11 O WPIC_OSC_EN
D8
TOUT12
E6
TOUT13 O GCAP3_STANDBY
E7
TOUT14
E8
TOUT15 O RX_ACQ
K2 32.768 kHz Input
CKIL
K4 16.8 MHz Input
CKIH
L2
CKOH
C423 PWM2_1.8V_FLTR
M3 1
TP403
CKO
6.8n U405
R10
R407
MUX_CTRL=0
PCAP
T10
PVCC Gen Port Ctrl Reg (GPCR) Gen Port Ctrl Reg (GPCR)
P10
GPCR = xxxxxxxx x00xxx00 GPCR = xxxxxxxx x11xxx11
PGND 47.
N10
GPCR (Bit7)=0
P1GND
C422 C415
SYMBOL 8-Wire RS232 4-Wire RS232
F16
MUX_CTL 10.n 10uF
PIN NAME ESSI
F13 CTS CTS CTS
CTSA_MCU_DE
G13
RTS RTS RTS
G14
RX RX RX
RXA_IC1_TDI
G15 TX TX TX
TXA_TDO
Internal Pulldown
L12
CTSB TP412
K12
RTSB TP411 NOTE: RESETS FROM THE BOTTOM CONNECTOR WILL ONLY BE POSSIBLE IF
J12
RXB TP407
MUX_CTRL =1 AND THE 8-WIRE INTERFACE IS THUS SET TO JTAG MODE
K11
TP408
TXB
J13 ROW7 RI SCKA
J16
ROW6 DCD SC2A
N13
INT7 DTR SRDA
COLUMN0 O KP_COL0
R14 INT6 DSR STDA
COLUMN1 O KP_COL1
R15
COLUMN2 O KP_COL2
T14
COLUMN3 O KP_COL3
R16
COLUMN4 O KP_COL4
P16
COLUMN5
P15
KEYPAD
COLUMN6_OC1
P14
COLUMN7
L15
ROW0 I KP_ROW0
K13
ROW1 I KP_ROW1
K14
ROW2 I KP_ROW2
K15
TP414
ROW3 I KP_ROW3
J14
ROW4 I KP_ROW4
J15
ROW5_IC2B C430
100.n
R13
RESET_IN R417
P13
6.8K
RESET_OUT
T13
STO
BAT_DATA
DISPLAY RS
RESET_OUT RESET_OUT
TX_DETECT
Connect to GCAP3 WDI Pin
AUDIO_IN
SWB+ Voltage enable for the CE bus
32.768 kHz Input
32KHz_CLK
I
16.8 MHz Input
I 16.8_MHz_CLK
MUX_CTRL=1
GPCR (Bit7)=1
SB9600 JTAG
ESSI
BUSY_OUT MCU_DE
O RS232_CTS
BUSY_IN (IC2) RESET_IN
I RS232_RTS
RX TDI
I RS232_RX
TX TDO
O RS232_TX
I MUX_CTRL
SCKA TCK
O RS232_RI
SC2A DSP_DE
O RS232_DCD
SRDA TMS
O RS232_DTR
STDA TRST
I RS232_DSR
TP405
TCXO_WARP
TCXO_WARP
O
I BAT_DATA
O DISPLAY_RS
O RESET_OUT
I TX_DETECT
O SOFT_TURN_OFF
AUDIO_SENSE
I
O SWB+_EN
O VIBR_EN
68P02963C70-O