AXIOMTEK SHB102 User Manual page 39

Intel core 2 quad/core 2 duo celeron processor picmg 1.3 full-size single board computer
Hide thumbs Also See for SHB102:
Table of Contents

Advertisement

SHB102 LGA775 SBC User's Manual
CPU Configuration
This screen shows the CPU Configuration, and you can change the value of the selected
option.
Hardware Prefetcher
This item automatically analyzes its requirements and prefetches data and instructions from
the memory. When enabled, the processor's hardware prefetcher will be allowed to
automatically prefetch data and code for the processor.
Adjacent Cache Line Prefetch
This item has a hardware adjacent cache line prefetch mechanism that automatically fetches
extra cache line whenever the processor requests for a cache line. This reduces cache latency
by making the next cache line immediately available if the processor requires it as well.
When enabled, the processor will retrieve the currently requested cache line, as well as the
subsequent cache line.
When disabled, the processor will only retrieve the currently requested cache line.
Max CPUID Value Limit
You can enable this item to let legacy operating systems boot even without support for CPUs
with extended CPU ID functions.
Execute-Disable Bit Capability
This item helps you enable or disable the No-Execution Page Protection Technology.
PHOENIX-AWARD BIOS Utility
33

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SHB102 and is the answer not in the manual?

Table of Contents