System Block Diagram - Supero SUPERSERVER 5018R-M User Manual

S S
UPER ERVER 5018R-M/5018R-MR User's Manual
Note: This is a general block diagram. Please see Chapter 5 for details.
SLOT3
PCIe3.0 x8
SLOT4 PCIe3.0 x8
SLOT5 PCIe3.0 x8
(x4 in x8)
LAN3
RJ45
RTL8211E-VB-CG
DDR3
SPI
BMC Boot Flash
SPI
BIOS
VGA CONN
Temp Sensor
EMC1402-1 *2 at diff SMBUS
Figure 1-1. Intel C610 Express Chipset:

System Block Diagram

0-8
0-7
0-6
0-5
PCI-E X8 Gen3
PCI-E X8 Gen3
PCI-E X4 Gen3
RJ45
LAN
i350
RJ45
5 6
1 2
USB 3.0
RGRMII
PCI-E X1 Gen2
BMC
USB 2.0
AST2400
SPI
LPC
COM1 COM2
Connector Header
VR12.5
5 PHASE
145W
Skt-R3
LGA2011-3
1 3A/B 3C 3D 2
DMI2
PCI-E X16 Gen3
DMI2
PCI-E X4 Gen2
1/2/3/4
5/6
PCH
7
13 USB2.0
SPI
TPM HEADER BIOS
HEADER
Debug Card
SYSTEM POWER
FAN SPEED
FRONT PANEL
CTRL
1-4
0-4
0-3
0-2
0-1
PCIe3.0 x16
PCI-E X4 Gen2
PCIe2.0 x8
SLOT2
(x4 in x8)
PCI-E X2 Gen2
PCIe2.0 x8
SLOT1
(x2 in x8)
8 9
6 7
5 4
3 2
1 0
6.0 Gb/S
6 7
4 5
2 3
0 1
USB 2.0
SLOT6