Yamaha Clavinova CVP-405 Service Manual page 39

PIN OUTER
NAME I/O
NO. NO.
211 AB22 VSS - Ground
212 AC23 VDD1 - Power supply +1.5 V
213 AD24 DMAL1 O Address bus (DIMM, SDRAM)
214 AE25 DCSL2 O Wave memory chip select (Low)
215 AF26 DRAS0 O DIMM, SDRAM row address strobe (RAS signal)
216 AC22 DCAS0 O DIMM, SDRAM column address strobe (CAS signal)
217 AB21 VDD3 - Power supply +3.3 V
218 AD23 DCLKIN I DIMM, SDRAM clock input
219 AE24 DQML2 O MASK signal
220 AF25 DCSL3 O Wave memory chip select (Low)
221 AF24 DQML0 O MASK signal
222 AC21 VDD3 - Power supply +3.3 V
223 AB20 VSS - Ground
224 AD22 DWEN0 O DIMM, SDRAM write enable
225 AE23 DCLK0 O
DIMM, SDRAM clock signal
226 AF23 DCLK1 O
227 AC20 DCLKE O DIMM, SDRAM clock enable
228 AD21 HMD13 I/O Wave memory data bus (Upper data memory)
229 AB19 VSS - Ground
230 AC19 VDD3 - Power supply +3.3 V
231 AE22 HMD15 I/O
232 AF22 HMD14 I/O
Wave memory data bus (Upper data memory)
233 AD20 HMD10 I/O
234 AE21 HMD12 I/O
235 AB18 VDD1 - Power supply +1.5 V
236 AC18 VDD3 - Power supply +3.3 V
237 AD19 HMD7 I/O
238 AF21 HMD11 I/O
Wave memory data bus (Upper data memory)
239 AE20 HMD9 I/O
240 AF20 HMD8 I/O
241 AB17 VSS - Ground
242 AC17 VDD1 - Power supply +1.5 V
243 AD18 HMD4 I/O
244 AE19 HMD6 I/O
Wave memory data bus (Upper data memory)
245 AF19 HMD5 I/O
246 AE18 HMD3 I/O
247 AB16 VSS - Ground
248 AC16 VSS - Ground
249 AD17 HMD1 I/O
250 AF18 HMD2 I/O Wave memory data bus (Upper data memory)
251 AE17 HMD0 I/O
252 AF17 DCSH0 O Wave memory chip select (High)
253 AB15 VSS - Ground
254 AC15 VDD3 - Power supply +3.3 V
255 AD16 DCSH1 O Wave memory chip select (High)
256 AE16 DQMH3 O
MASK signal
257 AF16 DQMH1 O
258 AD15 DMAH14 O
Address bus (DIMM, SDRAM)
259 AE15 DMAH13 O
260 AB14 VSS - Ground
261 AC14 VSS - Ground
262 AD14 DMAH11 O
263 AF15 DMAH12 O
264 AE14 DMAH10 O Address bus (DIMM, SDRAM)
265 AF14 DMAH9 O
266 AF13 DMAH8 O
267 AB13 VDD3 - Power supply +3.3 V
268 AC13 VDD3 - Power supply +3.3 V
269 AD13 DMAH6 O
270 AE13 DMAH7 O
Address bus (DIMM, SDRAM)
271 AE12 DMAH4 O
272 AD12 DMAH3 O
273 AC12 VDD3 - Power supply +3.3 V
274 AB12 VSS - Ground
275 AF12 DMAH5 O
276 AF11 DMAH2 O
Address bus (DIMM, SDRAM)
277 AE11 DMAH1 O
278 AD11 DMAH0 O
279 AC11 VSS - Ground
280 AB11 VSS - Ground
281 AF10 DRAS1 O DIMM, SDRAM row address strobe (RAS signal)
282 AE10 DCSH2 O Wave memory chip select (High)
283 AF9 DQMH2 O MASK signal
284 AD10 DCSH3 O Wave memory chip select (High)
285 AC10 VDD1 - Power supply +1.5 V
286 AB10 VSS - Ground
287 AE9 DQMH0 O MASK signal
288 AF8 DWEN1 O DIMM, SDRAM write enable
289 AD9 DCAS1 O DIMM, SDRAM column address strobe (CAS signal)
290 AE8 DCLK2 O DIMM, SDRAM clock signal
291 AC9 VDD3 - Power supply +3.3 V
292 AB9 VDD1 - Power supply +1.5 V
293 AD8 DCLK3 O DIMM, SDRAM clock signal
294 AF7 MELO0 O
295 AE7 MELO1 O MEL wave data output
296 AD7 MELO2 O
297 AC8 VDD3 - Power supply +3.3 V
298 AB8 VSS - Ground
299 AF6 MELO3 O
300 AE6 MELO4 O
301 AF5 MELO5 O MEL wave data output
302 AC7 MELO6 O
303 AD6 MELO7 O
304 AB7 WCLK0 O
For DAC word clock
305 AC6 WCLK1 O
306 AE5 EIRQ O E bus interrupt request
307 AF4 EICN O E bus initial clear
308 AD5 ESDA I/O E bus data
309 AE4 ESCL I/O E bus clock
310 AB6 MELI0 I
311 AC5 MELI1 I
312 AD4 MELI2 I
MEL wave data input
313 AF3 MELI3 I
314 AE3 MELI4 I
315 AF2 MELI5 I
PIN
FUNCTION
NO.
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
CVP-405/CVP-405PE/CVP-405PM
OUTER
NAME I/O
NO.
AB5 VSS - Ground
AC4 VDD1 - Power supply +1.5 V
AD3 MELI6 I
MEL wave data input
AE2 MELI7 I
AF1 ADLR O For ADC word clock
AB4 DITo O Digital audio output
AA5 VSS - Ground
AC3 AFRM I/O Frame signal (ABUS)
AD2 ACLK I/O Clock signal (ABUS)
AE1 ADIR O Direction signal (ABUS)
AD1 ADAT0 I/O Data bus (ABUS)
AA4 VDD3 - Power supply +3.3 V
Y5 ADAT9 I/O
AB3 ADAT3 I/O
AC2 ADAT1 I/O
Data bus (ABUS)
AC1 ADAT2 I/O
Y4 ADAT10 I/O
AA3 ADAT6 I/O
W5 VSS - Ground
W4 VDD3 - Power supply +3.3 V
AB2 ADAT4 I/O
AB1 ADAT5 I/O
Y3 ADAT11 I/O
AA2 ADAT7 I/O
V5 ADAT14 I/O Data bus (ABUS)
V4 ADAT15 I/O
W3 ADAT13 I/O
AA1 ADAT8 I/O
Y2 ADAT12 I/O
Y1 TDI I Test pin
U5 VSS - Ground
U4 VDD1 - Power supply +1.5 V
V3 HRD13 I/O
W2 HRD15 I/O
W1 HRD14 I/O
V2 HRD12 I/O
T5 HRD7 I/O
DRAM data bus
T4 HRD6 I/O
U3 HRD10 I/O
V1 HRD11 I/O
U2 HRD9 I/O
U1 HRD8 I/O
R5 VSS - Ground
R4 VDD3 - Power supply +3.3 V
T3 HRD5 I/O
T2 HRD4 I/O
T1 HRD3 I/O DRAM data bus
R3 HRD2 I/O
R2 HRD1 I/O
P5 VDD3 - Power supply +3.3 V
P4 HRD0 I/O DRAM data bus
P3 RWEN O DRAM write enable
R1 RQML O MASK signal (SDRAM)
P2 RCAS O DRAM column address strobe (CAS signal)
P1 RRAS O DRAM row address strobe (RAS signal)
N1 RA13 O DRAM address bus
N5 VDD3 - Power supply +3.3 V
N4 VDD3 - Power supply +3.3 V
N3 RA10 O
N2 RA12 O
DRAM address bus
M2 RA1 O
M3 RA2 O
M4 VDD3 - Power supply +3.3 V
M5 VSS - Ground
M1 RA0 O
L1 RA3 O
DRAM address bus
L2 RA4 O
L3 RA5 O
L4 VSS - Ground
L5 VSS - Ground
K1 RA6 O
K2 RA7 O
DRAM address bus
J1 RA9 O
K3 RA8 O
K4 VDD1 - Power supply +1.5 V
K5 VSS - Ground
J2 RA11 O DRAM address bus
H1 RCLK O SDRAM clock signal
J3 RCLKE O SDRAM clock enable
H2 RCLKIN I SDRAM, DRAM clock input
J4 VDD3 - Power supply +3.3 V
J5 VDD1 - Power supply +1.5 V
H3 RQMH O MASK signal (SDRAM)
G1 LRD15 I/O
G2 LRD14 I/O DRAM data bus (Lower data)
G3 LRD13 I/O
H4 VDD3 - Power supply +3.3 V
H5 VSS - Ground
F1 LRD12 I/O
F2 LRD11 I/O DRAM data bus (Lower data)
E1 LRD8 I/O
G4 VDD3 - Power supply +3.3 V
F3 LRD10 I/O DRAM data bus (Lower data)
G5 VDD3 - Power supply +3.3 V
F4 LRD9 I/O
E2 LRD7 I/O
D1 LRD5 I/O DRAM data bus (Lower data)
E3 LRD6 I/O
D2 LRD4 I/O
F5 VSS - Ground
E4 VSS - Ground
D3 LRD3 I/O
C1 LRD2 I/O
DRAM data bus (Lower data)
C2 LRD1 I/O
B1 LRD0 I/O
FUNCTION
39