JVC LT-42HB1BU Service Manual page 59

MAIN PWB CIRCUIT DIAGRAM (37/46) [STi7103 DEBUG PORT and RESET S/W]
1
JTAG Open drain output
A
MAIN PWB(31/46)
B
MAIN PWB(7/46)
ST_RESET
C
D
All location are from 1361 to 1380
1
2
ST_3V3
R1374
472/1005
R1367 R1367
Q1361
1
DCU_nRESET
MMBT4401
473/1005 473/1005
R1373
331/1005
ST_RESET R1371 103/1005
1
Q1363
MMBT4401
R1376
103/1005 1 2
3 4
S1361
OPEN-JTP1127WEM
+3V3_STI7103
+3V3_STI7103
R1364
332/1005
RS232_TXD3
MAIN PWB(36/46)
RS232_RXD3
2
(No.YA707<Rev.001>)2-81
3 4
ST_3V3
R1361
472/1005
R1362
Q1362
1
MMBT4401
103/1005
ST_3V3
R1370
472/1005
R1372
Q1364
1
MMBT4401
103/1005
C1366
104p/16V/1005
1
2
JP1362
OPEN-HEADER 2P
R1375
MAIN PWB(5/46) 1
M_RST_N
OPEN-102/1005
+5V
MAIN PWB ASS'Y(37/46)
R1365
R1363
[STi7103 DEBUG PORT and RESET S/W]
332/1005
Q1369
472/1005
FDV301N_NL
2 3 HU-71100006
+5V
R1368
Q1365
FDV301N_NL
472/1005
+5V
2 3
JP1361
1
2
3
4
C1365
OPEN-53014-0410
104p/16V/1005
DEBUG PORT 1
3 4
2-82(No.YA707<Rev.001>)
5
MAIN PWB(31/46)
STb7100_nRESET
Q1366
OPEN-MMBT4401
5
6
A
B
C
D
6
hb1_main_0612_38/48_0.0