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MAIN PWB CIRCUIT DIAGRAM (8/46) [Flash and CI Interface]
5
U102C
FLI10620H
Flash_WP#
W1
OOB_CTX
W2
OOB_CRX
W3
OOB_DRX
D
POD_DET#
AD4
POD_DET#
POD_DETEC_N
POD_DAT_DIR
AD5
POD_DAT_DIR
POD_DIR_N
POD_A4
AE3
POD_A4
POD_A4_CTX
POD_A5
AF3
MAIN PWB(9/46)
POD_A5_ITX
POD_A5
POD_A6
AF2
POD_A6
POD_A6_ETX
POD_A7
AG2
POD_A7
POD_A7_QTX
POD_A8
AF1
POD_A8
POD_A8_CRX
POD_A9
AG1
POD_A9
POD_A9_DRX
POD_A14
W5
POD_A14
POD_A14_MCLKO
MUX_TSI_CLK
W6
MUX_TSI_CLK
POD_VS2_MCLKO
MUX_TSI_VAL
Y5
MUX_TSI_VAL
POD_BVD2_MOVAL
MUX_TSI_SYNC
Y4
MUX_TSI_SYNC
POD_BVD1_MOSTRT
MUX_TSI_D7
AB1
MUX_TSI_D7
POD_D15_MDO7
MUX_TSI_D6
AA1
MUX_TSI_D6
MAIN PWB
POD_D14_MDO6
MUX_TSI_D5
Y1
MUX_TSI_D5
POD_D13_MDO5
(9/46),(24/46)
MUX_TSI_D4
AB2
MUX_TSI_D4
POD_D12_MDO4
MUX_TSI_D3
AA2
MUX_TSI_D3
POD_D11_MDO3
MUX_TSI_D2
Y2
MUX_TSI_D2
POD_D10_MDO2
MUX_TSI_D1
AA3
MUX_TSI_D1
POD_D9_MDO1
MUX_TSI_D0
Y3
C
MUX_TSI_D0
POD_D8_MDO0
CI_WAIT_N
V3
CI_WAIT_N
POD_WAIT_N
MAIN PWB(10/46)
CI_CD1_N
V5
CI_CD1_N
POD_CD1
CI_CD2_N
V4
CI_CD2_N
POD_CD2
CI_CE1_N
MAIN PWB(9/46)
AE4
CI_CE1_N
POD_CE_1
W4
POD_CE_2
CI_IRQ_N
V2
CI_IRQ_N
POD_READY_IRQ_N
CI_RESET
MAIN PWB(10/46)
V1
CI_RESET
POD_RESET
Bootstrap
Pin Name
BSTRAP_BOOT_MODE
POD_HOST_A0
POD_HOST_A1
B
BSTRAP_EXT_OSC
POD_HOST_A2
BSTRAP_16BIT_FLASH
POD_HOST_A3
BSTRAP_NAND_FLASH_EN
POD_HOST_A4
BSTRAP_PAGESIZE
POD_HOST_A5
BSTRAP_NAND_FLASH_DWIDTH
POD_HOST_A6
A
BSTRAP_NOR_FLASH_SEL
POD_HOST_A7
All location are from 181 to 220
5
4
HOST_D[15..0]
HOST_D0
AG7
POD_HOST_D0/SPI_SDI
HOST_D1
AJ8
POD_HOST_D1
HOST_D2
AG8
POD_HOST_D2
HOST_D3
AE7
POD_HOST_D3
HOST_D4
AH9
POD_HOST_D4
HOST_D5
AF9
POD_HOST_D5
AJ10
HOST_D6
POD_HOST_D6
HOST_D7
AG10
POD_HOST_D7
HOST_D8
AF7
HOST_D8
HOST_D9
AH8
HOST_D9
HOST_D10
AE8
HOST_D10
HOST_D11
AJ9
HOST_D11
HOST_D12
AG9
HOST_D12
HOST_D13
AE9
HOST_D13
HOST_D14
AH10
HOST_D14
HOST_D15
AF10
HOST_D15
HOST_A[24..0]
HOST_A0
AJ15
POD_HOST_A0
HOST_A1
AH15
POD_HOST_A1
AG15
HOST_A2
POD_HOST_A2/SPI_SDO
HOST_A3
AE14
POD_HOST_A3/SPI_CLK
HOST_A4
AF14
POD_REG_HOST_A4
HOST_A5
AG14
POD_IOWR_HOST_A5
HOST_A6
AH14
POD_IORD_HOST_A6
HOST_A7
AJ14
HOST_A7
HOST_A8
AE13
HOST_A8
HOST_A9
AF12
HOST_A9
HOST_A10
AG12
POD_HOST_A10
HOST_A11
AH12
POD_HOST_A11
HOST_A12
AJ12
POD_HOST_A12
HOST_A13
AE11
POD_HOST_A13
AF11
HOST_A14
HOST_A14
HOST_A15
AG11
HOST_A15
HOST_A16
AH11
HOST_A16
HOST_A17
AE10
HOST_A17
HOST_A18
AF13
HOST_A18
HOST_A19
AG13
HOST_A19
HOST_A20
AE12
HOST_A20
HOST_A21
AD13
HOST_A21
HOST_A22
AH13
HOST_A22
HOST_A23
AJ11
HOST_A23
HOST_A24
AD9
HOST_A24
R189
330/1005
HOST_WE#
AJ13
POD_WE_HOST_WR
AF8
R193
330/1005
HOST_OE#
POD_OE_HOST_RD
HOST_ACK
AG3
HOST_ACK
AE5
HOST_DEV_CS2_N
AF4
HOST_DEV_CS1_N
HOST_CS0#
AJ4
HOST_CS0#
HOST_DEV_CS0_N
R199
000/1005
AG6
HOST_BOOT_CS_N
HOST_BOOT_CS#
HOST_RD
AH5
HOST_READY
Description
Pins POD_HOST_A[1:0] indicate on chip
hardware the host interface configuration
to use after hard reset:
MAIN PWB ASS'Y(8/46)
A1;A0 = 00 = Function test, vendor mode.
A1;A0 = 01 = Function test, vendor mode.
A1;A0 = 10 = Boot from FLASH
A1;A0 = 11 = Boot from IROM
[Flash and CI Interface]
Pin POD_HOST_A2 indicates:
0 = Internal osc
1 = External osc
HU-71100006
Pin POD_HOST_A3 indicates type of
memory for external boot FLASH.
0 = 8-bit FLASH
1 = 16-bit FLASH
Pin PODREG_HOST_A4 indicates type of
memory for external boot FLASH.
0 = NOR FLASH
1 = NAND FLASH
Pin POD_IOWR_HOST_A5 indicates page
size for off chip NAND FLASH.
0 = Small page NAND FLASH
1 = Large page NAND FLASH
Pin POD_IORD_HOST_A6 indicates data
width for NAND FLASH (used by IROM
boot s/w only).
0 = 8-bit NAND FLASH
1 = 16-bit NAND FLASH
Pin HOST_A[7] selects whether parallel
NOR flash or SPI flash is used for boot
when BSTRAP_BOOT_MODE=10 (IROM
bypass). Ignored if
BSTRAP_BOOT_MODE != 10.
0 = boot from parallel NOR flash
1 = boot from SPI flash
4
(No.YA707<Rev.001>)2-23
3
C184
104p/16V/1005
+3V3_A
L182
BLM18PG300SN1D
MAIN PWB(9/46),(45/46),(46/46)
HOST_A1
HOST_A2
HOST_A3
HOST_A4
HOST_A5
HOST_A6
HOST_A7
HOST_A8
HOST_A9
HOST_A10
HOST_A11
HOST_A12
HOST_A13
HOST_A14
HOST_A15
HOST_A16
HOST_A17
HOST_A18
HOST_A19
HOST_A20
HOST_A21
HOST_A22
HOST_A23
R203
000/1005
HOST_A24
R204
000/1005
TP181
1
PCB_TP08
+3V3_A
Flash_WP#
MAIN PWB(9/46)
HOST_WE#
HOST_OE#
MAIN PWB(9/46),(46/46)
R206
472/1005
MAIN PWB(45/46)
MAIN PWB(45/46),(46/46)
HOST_BOOT_CS#
NOTE.
64 MBit FLASH : R203, R204, L26 OPEN
128 MBit FLASH : R204, L26 OPEN
256 MBit FLASH : L27 OPEN(P30 Series)
+3V3_A
R234
HOST_WE#
103/1005
R220
HOST_A23
103/1005
R217
HOST_A24
103/1005
A24 setting default value "0" when STi7103 access flash
HOST WE# setting default value "1" when STi7103 access flash
3
2-24(No.YA707<Rev.001>)
2
+3V3_A
C185
C183
104p/16V/1005
104p/16V/1005
C182
C181
104p/16V/1005
106p/10V/2012
PC28F256P33BF/BGA
U181
HOST_D0
A1
F2
A1
DQ0
HOST_D1
B1
E2
A2
DQ1
HOST_D2
C1
G3
A3
DQ2
HOST_D3
D1
E4
A4
DQ3
HOST_D4
D2
E5
A5
DQ4
HOST_D5
A2
G5
A6
DQ5
HOST_D6
C2
G6
A7
DQ6
HOST_D7
A3
H7
A8
DQ7
HOST_D8
B3
E1
A9
DQ8
C3
E3
HOST_D9
A10
DQ9
HOST_D10
D3
F3
A11
DQ10
HOST_D11
C4
F4
A12
DQ11
HOST_D12
A5
F5
A13
DQ12
HOST_D13
B5
H5
A14
DQ13
HOST_D14
C5
G7
A15
DQ14
HOST_D15
D7
E7
A16
DQ15
D8
A17
A7
A18
B7
A19
MAIN PWB(45/46)
C7
A20
C8
A21
A8
B4
#CS_FLASH_DG
#CS_FLASH_DG
A22
CE
HOST_OE#
G1
F8
A23
OE
HOST_WE#
H8
G8
A24
WE
B6
C6
NC(A25)
WP
F6
ADV
H1
E6
RFU1
CLK
G2
RFU2
F1
RFU3
R181
E8
RFU4
330/1005
B8
D4
RFU5
RST
PWR_/RESET
A4
F7
VPP
WAIT
MAIN PWB(6/46)
POD_DET#
R184
OPEN-103/1005
HOST_BOOT_CS#
R182
103/1005
HOST_RD
R183
472/1005
HOST_ACK
R205
103/1005
BOOT STRAP SETTING
R187
103/1005
HOST_A0
R188
HOST_A1
R190
R191
103/1005
HOST_A2
R192
HOST_A3
R194
R195
103/1005
HOST_A4
R196
R197
103/1005
HOST_A5
R198
HOST_A6
R200
R201
103/1005
HOST_A7
R202
2
1
D
+3V3_A
R185
103/1005
R186
Flash_WP#
C
+3V3_A
B
+3V3_A
OPEN-103/1005
103/1005
OPEN-103/1005
103/1005
OPEN-103/1005
OPEN-103/1005
103/1005
OPEN-103/1005
A
1
hb1_main_0612_6/48_0.0
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