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MAIN PWB CIRCUIT DIAGRAM (31/46) [STi7103 CLOCKS, RESET and DEBUG]
5
D
ST_3V3
JP1211
C
2
1
4
3
6
5
8
7
10
9
12
11
R1217
14
13
16
15
18
17
20
19
OPEN-470/1005
OPEN_HE10_20CM
R1213
103/1005
B
A
All location are from 1211 to 1230
5
4
R1223
OPEN-472/1005
R1211
R1221
R1224
C1215
104p/16V/1005
103/1005
OPEN-472/1005
472/1005
TrigOut_ST
TrigIn_ST
nASEBRK_ST
TMS_ST
TCK_ST
TDI_ST
TDO_ST
JTAG_nRESET
MAIN PWB(37/46)
DCU_nRESET
nTRST_ST
R1225
R1214
R1215
R1216
103/1005
103/1005
103/1005
103/1005
4
(No.YA707<Rev.001>)2-69
3
R1219
103/1005
MAIN PWB(37/46)
C1216
102p/50V/1005
U1131C
ST_2V6
A1
C1213
sysaclkin
R1218
R1218
G24
090p/50V/1005
sysbclkinalt
100/F/1005
C1214
Y1211
AM25
sysbclkin
27MHz/13.5pF/SMD
AL25
sysbclkosc
1
H23
TP1211 PCB_TP08
090p/50V/1005
rtcclkin
1
C21
TP1212 PCB_TP08
tmuclk
nTRST_ST
D21
nottrst
TDO_ST
D23
tdo
nASEBRK_ST
B21
notasebrk
TMS_ST
C22
tms
TDI_ST
C23
tdi
TrigOut_ST
A22
triggerout
TrigIn_ST
B22
triggerin
TCK_ST
C24
tck
ST_3V3
ST_3V3
C1211
C1212
104p/16V/1005
104p/16V/1005
MAIN PWB ASS'Y (31/46)
[STi7103 CLOCKS, RESET and DEBUG]
HU-71100006
3
2-70(No.YA707<Rev.001>)
2
ST_3V3
STb7100_nRESET
ST-7103AUD
A24
notresetin
E24
1
TP1213 PCB_TP08
wdogrstout
AG24
sysitrq[0]
AH25
sysitrq[1]
AF25
sysitrq[2]
AG26
sysitrq[3]
E20
nmi
E22
1
TP1214 PCB_TP08
sysclkout
System&Debug
2
1
D
R1212
R1222
103/1005
103/1005
C
B
A
1
hb1_main_0612_31/48_0.0
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