JVC LT-42HB1BU Service Manual page 28

MAIN PWB CIRCUIT DIAGRAM (6/46) [USB,I2C,JTAG]
5
UART0 : PC Display Debug message
UART1 : G-Probe application run at PC
D
+3V3_A
FLI_SDA_1
MAIN PWB(2/46),(26/46),(27/46)
FLI_SCL_1
FLI_SDA_0
MAIN PWB(5/46),(17/46),(22/46),(40/46)
FLI_SCL_0
UART0_RX
MAIN PWB(36/46) STi7103_UART
UART0_TX
UART1_RX
MAIN PWB(23/46)
UART1_TX
MAIN PWB(17/46) FRC_/RST
P_DIM
MAIN PWB(3/46)
A_DIM
MAIN PWB(10/46)
CI_PWR
MAIN PWB(5/46) FLI_INT
C
C117
104p/16V/1005
+3V3_A
R128
622/F/1005
B
C125
5R0p/50V/1005
R133
OPEN-153/1005
+5V
R138
103/1005
A
R137
103/1005
All location are from 111 to 160
5
4
R113 222/1005
R115 222/1005
R116 222/1005 U102G
R117 222/1005 FLI10620H
FLI_SDA_1 R120 330/1005
D21
2WIRE_M1_SDA_UART2_TX
FLI_SCL_1 R118 330/1005
D20
2WIRE_M1_SCL_UART2_RX
FLI_SDA_0 R119 330/1005
F20
2WIRE_M0_SDA
FLI_SCL_0 R121 330/1005
E20
2WIRE_M0_SCL
UART0_RX
A19
UART0_RXD
UART0_TX
B19
UART0_TXD
UART1_RX
A20
UART1_RXD
UART1_TX
B20
UART1_TXD
C20
UART1_RTS
TP113
1 C19
UART1_CTS
PCB_TP08
A13
PWM3
B13
PWM2_GPIO6
C13
PWM1_GPIO5_/INT5
D13
PWM0_GPIO4_/INT4
C29
USB_FLAG
C28
USB_PWREN
USB_D0+
AJ20
USBPHY_PADP
USB_D0-
AH20
USBPHY_PADM
DFSYNC_IN_OUT_GPIO8
AG20
USBPHY_VRES
AG19
C119 C121 USB_AVDD33
AH19
105p/16V/1005 104p/16V/1005 USB_AVDD33
L111
AF20
USB_AVDD33
BLM18PG300SN1D
C118
AF19
USB_GND
47uF/16V/MVK/S
AJ19
USB_GND
AD20
C120
USB_GND
104p/16V/1005
JP112
+5V_USB
KJA-UB-4-0004
L113
ACM2012H-900
1
1 2 2
3
4 3 4
RV111
C126
OPEN-AVRL161A1R1NTB
5R0p/50V/1005
RV112
OPEN-AVRL161A1R1NTB
R134
OPEN-153/1005
+5V
C127
106p/10V/2012
R139
000/1005 U114
L114
1 5
EN OUT
4
BLM21PG600SN1D
IN
3 2
FLG GND
R5523N USB HIGH-SIDE POWER SWITCH
C128
Active high
104p/16V/1005
4
(No.YA707<Rev.001>)2-19
3
+3V3_A
R111
OPEN-104/1005
C112
OPEN-680p/50V/1005
R114
OPEN-104/1005
A26 1
OTP_VDD33
TP112
PCB_TP08
D23
RESET_N
Y111
R122 000/1005
A22 1 2
REF_CLK
A23
XTAL_IN
19.6608MHZ/
TP111
E12 1 20PF/SX-1/SMD
CLKOUT
R124
PCB_TP08
NVRAM_WP
F21 OPEN-000
OBUFC_CLK
C113
270p/50V/1005
TRST#
B26
TRST
TDI
B27
TDI
TDO
A27
TDO
TMS
A28
TMS
TCK
B28
TCK
EJTAG_RST#
A29
EJ_RST_N
B29 DINT
EJ_DINT
E13
BLT_EN
+3V3_A
R129 OPEN-472/1005
C27
TESTMODE0
R130 OPEN-472/1005
C26
TESTMODE1
+1V2
L112
AE20
USB_AVDD12
BLM18PG300SN1D
C124
C123
104p/16V/1005
106p/10V/2012
5
VBUS SGND
1
D-
2
D+
3
6
GND SGND
4
+5V_USB
C129
100uF/16V/MVK/S
3
2-20(No.YA707<Rev.001>)
2
+3V3_A
U111
OPEN-ASM811REUSF-T
1 4
GND VCC
2 3
RESET MR LPM_RST_N
Reset Threshole
S111
: +3.08V
1 2
R112 000/1005
3 4
OPEN-JTP1127WEM
MAIN PWB(8/46)
PWR_/RESET
+3V3_A
R123 102/1005
PR111 103*4/1005
1 8
2 7
C114
3 6
270p/50V/1005
4 5
+3V3_A
R125 OPEN-200/1005
R127
R126 102/1005
C115 200p/50V/1005
MAIN PWB(3/46)
103/1005
EEPROM
Address:0xA4/A5 +3V3_A
C122
104p/16V/1005
U113
1 8
A0 VCC
WP
2 7
A1 WP
FLI_SCL_0
3 6
A2 SCL
FLI_SDA_0
4 5
VSS SDA
24LC256
+5V
R135
OPEN-472/1005
JP113
1
2
3
4
OPEN-53014-0410
MAIN PWB ASS'Y(6/46)
[USB,I2C,JTAG]
HU-71100006
2
1
D
MAIN PWB(5/46)
JP111
OPEN-2110-DS14-G
1 2
3 4
5 6
7 8
C
9 10
+3V3_A
11 12
13 14
C116
EJTAG
104p/16V/1005
+3V3_A
R131
103/1005
R132
103/1005
Q111 1 NVRAM_WP
MMBT4401
B
NVRAM_WP : H = Enable write
NVRAM_WP : L = Disable write
R136
OPEN-472/1005
UART0_TX
UART0_RX
A
1
hb1_main_0612_4/48_0.0