Yamaha QL5 Service Manual page 77

88E6350R (YD688A00) GIGABIT ETHERNET SWITCHING HUB
PIN
NAME I/O
NO.
1 I/O Column 3 for the LED
C3_LED
2 Media Dependent Interface [3]
P0_MDIN[3] I/O
Media Dependent Interface [3]
3 P0_MDIP[3] I/O
4 P0_AVDD - Power supply 1.8V
5 P0_MDIN[2] I/O Media Dependent Interface [2]
6 P0_MDIP[2] I/O Media Dependent Interface [2]
7 P0_MDIN[1] I/O Media Dependent Interface [1]
8 P0_MDIP[1] I/O Media Dependent Interface [1]
9 P0_AVDD - Power supply 1.8V
10 P0_MDIN[0] I/O Media Dependent Interface [0]
11 P0_MDIP[0] I/O Media Dependent Interface [0]
12 I/O Media Dependent Interface [3]
P1_MDIN[3]
13 Media Dependent Interface [3]
P1_MDIP[3] I/O
Power supply 1.8V
14 P1_AVDD -
15 P1_MDIN[2] I/O Media Dependent Interface [2]
16 P1_MDIP[2] I/O Media Dependent Interface [2]
17 P1_MDIN[1] I/O Media Dependent Interface [1]
18 P1_MDIP[1] I/O Media Dependent Interface [1]
19 P1_AVDD - Power supply 1.8V
20 P1_MDIN[0] I/O Media Dependent Interface [0]
21 P1_MDIP[0] I/O Media Dependent Interface [0]
22 P2_MDIN[3] I/O Media Dependent Interface [3]
23 I/O Media Dependent Interface [3]
P2_MDIP[3]
24 Power supply 1.8V
P2_AVDD -
Media Dependent Interface [2]
25 P2_MDIN[2] I/O
26 P2_MDIP[2] I/O Media Dependent Interface [2]
27 P2_MDIN[1] I/O Media Dependent Interface [1]
28 P2_MDIP[1] I/O Media Dependent Interface [1]
29 P2_AVDD - Power supply 1.8V
30 P2_MDIN[0] I/O Media Dependent Interface [0]
31 P2_MDIP[0] I/O Media Dependent Interface [0]
32 RESET - Resistor Current reference
33 AVDD - Gigabit PHY 1.8V power supply
34 - No Connect
NC
35 Ground
XTAL_GND -
No Connect
36 NC -
37 XTAL_IN I 25 MHz system reference clock input provided from the board
38 XTAL_OUT O Syatem reference clock output provided to the board
39 AVDD - Gigabit PHY 1.8V power supply
40 VDDO_CORE - 1.0V power supply to the digital core
41 VDDO_S - 3.3V power supply for I/O pins
42 PTP_TRIG/S_VDDOS I/O Precise Timing Protocol Trigger Generate/VDDO_S 0=2.5V 1=3.3V
43 -
VDDO_CORE 1.0V power supply to the digital core
44 I/O
P3_MDIN[3] Media Dependent Interface [3]
45 I/O
P3_MDIP[3] Media Dependent Interface [3]
46
P3_AVDD - Power supply 1.8V
47 P3_MDIN[2] I/O Media Dependent Interface [2]
48 P3_MDIP[2] I/O Media Dependent Interface [2]
49 P3_MDIN[1] I/O Media Dependent Interface [1]
50 P3_MDIP[1] I/O Media Dependent Interface [1]
51 P3_AVDD - Power supply 1.8V
52 P3_MDIN[0] I/O Media Dependent Interface [0]
53 P3_MDIP[0] I/O Media Dependent Interface [0]
54 I/O
P4_MDIN[3] Media Dependent Interface [3]
55 I/O
P4_MDIP[3] Media Dependent Interface [3]
56 -
P4_AVDD Power supply 1.8V
57
P4_MDIN[2] I/O Media Dependent Interface [2]
58 P4_MDIP[2] I/O Media Dependent Interface [2]
59 P4_MDIN[1] I/O Media Dependent Interface [1]
60 P4_MDIP[1] I/O Media Dependent Interface [1]
61 P4_AVDD - Power supply 1.8V
62 P4_MDIN[0] I/O Media Dependent Interface [0]
63 P4_MDIP[0] I/O Media Dependent Interface [0]
64 NC - No Connect
65 -
NC No Connect
PIN
FUNCTION
NO.
NAME I/O
66 SW_MODE[1] I
Switch Mode 00=Test mode 01=Reserved
10=Unmanaged/Forwarding mode 11=CPU Attached/Disable mode
67
SW_MODE[0] I Switch Mode 00=Test mode 01=Reserved
10=Unmanaged/Forwarding mode 11=CPU Attached/Disable mode
68 /RESET I Hardware reset
69 VDDO_CORE - 1.0V power supply to the digital core
70 MDC_CPU I Management Data Clock, Slave
71 MDIO_CPU I/O Management Data I/O, Slave
72 /INT - INTn is an active low, open drain pin
73 P5_RGMII_EN I Port5's GMII/RGMII/MII interface
enable(generically referred to as RGMII5)
74
VDDO_CORE - 1.0V power supply to the digital core
75
P5_VDDO - Power supply 3.3V
76
P5_OUTD[3] O Output Data
77
P5_OUTD[2] O Output Data
78 P5_OUTD[1] O Output Data
79 P5_OUTD[0] O Output Data
80 VDDO_CORE - 1.0V power supply to the digital core
81 P5_OUTEN/ O Output Enable
82 P5_GTXCLK O Transmit Clock
83 P5_OUTCLK I Output Clock
84 P5_VDDO - Power supply 3.3V
85
P5_INCLK I Input Clock
86
P5_INDV I Input Data Valid
87
VDDO_CORE - 1.0V power supply to the digital core
88
P5_IND[0] I Input Data
89 P5_IND[1] I Input Data
90 P5_IND[2] I Input Data
91 P5_IND[3] I Input Data
92 P5_VDDO - Power supply 3.3V
93 VDDO_CORE - 1.0V power supply to the digital core
94 P5_CRS I/O Carrier Sense
95 P5_COL I/O Collision
96
P6_RGMII_EN I Port6's GMII/RGMII/MII interface
enable(generically referred to as RGMII6)
97
VDDO_CORE - 1.0V power supply to the digital core
98
P6_VDDO - Power supply 3.3V
99 P6_OUTD[3] O Output Data
100 P6_OUTD[2] O Output Data
101 P6_OUTD[1] O Output Data
102 P6_OUTD[0] O Output Data
103 VDDO_CORE - 1.0V power supply to the digital core
104 P6_OUTEN/ O Output Enable
105 O Transmit Clock
P6_GTXCLK
106
P6_OUTCLK I Output Clock
107
P6_VDDO - Power supply 3.3V
108
P6_INCLK I Input Clock
109
P6_INDV I Input Data Valid
110 VDDO_CORE - 1.0V power supply to the digital core
111 P6_IND[0] I Input Data
112 P6_IND[1] I Input Data
113 P6_IND[2] I Input Data
114 P6_IND[3] I Input Data
115 P6_VDDO - Power supply 3.3V
116 - 1.0V power supply to the digital core
VDDO_CORE
117
P6_CRS I/O Carrier Sense
118
P6_COL I/O Collision
119
P0_LED/JUMBO O Parallel multiplexed LED output/JumboMode register
120
P1_LED/LED_SEL[0] O Parallel multiplexed LED output/
121 P2_LED/LED_SEL[1] O Parallel multiplexed LED output/Link/Activity with Speed select
122 EE_VDDO - Power supply 3.3V
123 P3_LED O Parallel multiplexed LED output
124 P4_LED O Parallel multiplexed LED output
125 O
C0_LED Column 0 for the LED
126 O
C1_LED Column 1 for the LED
127
EE_VDDO - Power supply 3.3V
128
C2_LED O Column 2 for the LED
129
VSS - Ground to device
QL5/QL1
QL5 DNT5: IC101
QL1 DNT1: IC101
FUNCTION
77