Yamaha QL5 Service Manual page 302

H G
BLOCK DIAGRAM 002 (QL5/QL1)
DSP32
DSP16
1
USB CN103(5P)
CN201
(5P)
See page 5
LCDC CN102(6P)
CN101
(6P)
See page 5
PN16M
I2C
CN505
(8P)
CN603(8P)
See page 6
2
FD1M
E-bus
CN002
(7P)
CN601(7P)
See page 6
FD2
E-bus
CN002
See page 6 (7P)
CN602(7P)
QL5 only
CN981(3P)
DCM
CN232
LAMP CNT
(3P)
See page 9
3
CN101
(180P)
CPUQL
CN601
(180P)
See page 5
DNT5
QL5
4
DNT1
QL1
Ethernet
(SCP/
Nuendo Extension)
Dante IN
8ch/line
QL5: *8
QL1: *4
/
/
CN221(38P),
Dante OUT
CN222(38P)
8ch/line
QL5: *8
QL1: *4
CN221(38P),
CN222(38P)
DANTE CLOCK
SPI, UART
5
See page 7
6
4 28CA1-2001135745-2
F E
QL5
QL1
USB
IC102,103(20P)
SCI
Master Clock
IC602(16P)
PCA
9516
IC601(16P)
PCA
9516
SCI
CAUTIONS
IC981(14P)
15MHz
IC114-117(20P), 2TR OUT
IC118, IC119(24P) 2ch/line
CPU bus
CPU IN/OUT
2ch/line
DSP block
Master Clock
IC554(100P)
See page 11
CPLD
Clock
IC553(30P)
SRC
MP3
IC552
DSP7
(144P)
DSP
QL5 *7
QL1 *5
IC221(48P)
FPGA (LAB)
Ethernet
PHONE OUT
MAC/PHY
DSP6 *4
SHARC *1
25MHz 60MHz X201
24.576MHz
X221
X101
FX
X151 X152
49.152 45.1584
MHz MHz
CPLD
(PLLPU)
IC151(144P)
PLL
IC157(14P)
D
CN751(40P)
IC651-659(20P)
Master Clock
IC751(20P)
IC801-804(20P)
ADIN
2ch/line
8or16
/
DAOUT
2ch/line
4or8
/
IC901, 902
2ch/line
(20P)
IC931(20P)
SLOT WCIN
2
/
BNC IN
Master Clock
C B
JK
IC101(28P)
DIT
CS8406
IC601, 602
(20P)
IC201, 202(20P)
Reg.
IC301(16P)
IC302(16P)
IC402(6P)
PC
CN601(40P)
IC401(16P)
CN751(40P)
Master Clock
HAAD
(INPUT 1-8)
Tx_CPU
ADIN 1-8,9-16,17-24,25-32
/RESET_ADA,/RESET_CPU
See page 8
CN801-804(23P) CN901(23P)
(INPUT 9-16)
(INPUT 17-24)
(INPUT 25-32)
Master Clock
DA
(OMNI OUT 1-8)
/RESET_ADA
DAOUT 1-8,9-16
See page 8
CN901(11P), CN901(11P),
CN902(8P), CN903(8P)
(OMNI OUT 9-16)
CN903(8P)
Master Clock
HP
PHONES L-R
(PHONES)
/RESET_ADA
CN931(12P) CN001(12P)
See page 8
BLOCK DIAGRAM 002 (QL5/QL1)
A
QL5/QL1
JK101
DIGITAL OUT
AES/EBU
CN201
GPI
JK301
IN
WORD CLOCK
OUT
JK302
IN
MIDI
OUT
JK401
QL5 only
QL5 only
QL5 only
DSP, FX, JK