Tektronix DC5010 Instruction Manual page 247

Theory of Operation-DC 501 0
U1810A and U1801 A (Channel A) and U1810B and U1801 B
(Channel B). Transistors Ql7O2, Ql7O1, Ql7O4, and
(21703, with associated circuitry, operate as fast ECL to LS
_
TTL converters. These converters provide drive for the fol-
lowing LS TTL stages and must operate reliably up to
25 MHz. The counts in these (and the preceeding) ECL
stages must also be converted to CMOS levels for eventual
readout by the microprocessor. However, since this conver-
sion occurs long after the count chains have stopped count-
ing and are stabilized, these translators need not be fast.
The comparators U1710A, B, C, D and U1102A, B, and C
have one input set at a voltage half-way between an ECL
high and low. This voltage is set by resistors R1712 and
R1710. With pull up resistors R1420 (fixed resistor net-
work), R1207, R1208 and R1209 tied to +5 volts, the ECL
transition from high to low (on the other input) results in a
full CMOS swing on the comparators output. This results in
a highly reliable translator that draws little power.
The next bit of each chain is a single LS TTL flip flop,
U1120A, Channel A (U1120B, Channel B). Following this IC
is an LS TTL 4-bit counter, U1113A, Channel A (U1113B,
Channel B) followed by a lower power CMOS 4-bit counter,
U1115A, Channel A (U1115B, Channel B). These stages,
too, must be read by the microprocessor. The LS TTL out-
puts are pulled high by the fixed resistor network, R1014, to
ensure valid CMOS levels to the serial readout circuitry. At
this point, the two accumulator chains lose their symmetry
(not for functional reasons but for more economical use of
the components). The Channel A accumulator uses the 16-
bit counter contained in U1410 (see Diagram 9). The Chan-
nel B accumulator (Diagram 4) uses 11 of the 12 bits
available in the CMOS counter, U1212. The circuitry, de-
scribed, provides a total of 29 hardwired bits for the Chan-
nel A accumulator and 24 hardwired bits for the Channel B
accumulator. Since each accumulator requires 43 bits, the
firmware counters supply 14 bits (Channel A) and 19 bits
(Channel B) respectively.
Five CMOS parallel-to-serial shift registers consisting of
U1121, U1114, U1122, U1211, and U1312 are used by the
microprocessor to read out the contents of the Channel A
and B accumulators. When the ILATCH control line (pin 9 of
each register) is brought high, data are applied into the reg-
isters asychronously with the clock. When pin 9 is brought
low again, data can be shifted into (pin 11 of each register)
and out of (pin 3 of each register) the registers synchronous-
ly with the positive transition of the SERIAL CLOCK signal
(pin 10 of each register).
Before each measurement is initiated by the micro-
processor, the MR (Master Reset) signal is asserted via pin
33 of U1410 (see Diagram 9). This reset signal is inverted by
U1520D (Diagram 4) applying to pin 1 of U1120A. The
-
MR signal is also inverted and buffered again by U1314D,
U1314F, and U1520E to provide an ECL, LS TTL, and
-
CMOS compatible reset signal (MR, signal also guarantees
the two synchronizer flip flops (located on Diagram 3),
U1000C and U1 OOOB, will begin set.
TlME BASE AND 32 MHz
PLL-DIAGRAM
6
The 10 MHz standard time base consists of a 10 MHz
crystal, Y1520, and a Colpitts oscillator circuit, Q1420, and
associated components. The frequency of the standard time
base is adjusted by variable capacitor, C1521 (accessed
through the instrument's back plate).
The Option 01 high stability time base consists of a self
contained, oven controlled 10 MHz oscillator, Y1530. This
time base is adjusted via a hole in the rear of the case
(accessed through the instrument back plate). The 18 volts
input to the time base is derived from the fused +26 volts in
the power module and regulated by a three-terminal regula-
tor circuit, U1430, and associated components.
NOTE
The single-starred schematic diagram 5 components
for the standard time base circuit are removed if the
Option 01 time base circuit is installed.
The 10 MHz output signal from either the internal time
bases or an external source (1, 5, 10 MHz) is applied to the
base of Q1500. The buffered signal at the collector of
Q1500 can be either 1 MHz, 5 MHz or 10 MHz. This signal
is buffered again by U1500F. If the input signal frequency is
1 MHz, jumper plug P I 51 0 (located on the Auxiliary board)
connects pins 4 and 5 of J1510. A 5 MHz external input
signal requires that IC U1411 divide-by-five (s5), therefore,
P I 51 0 connects J1510 pins 2 and 3 or pins 3 and 4. A
10 MHz time base signal requires U1411 to divide-by-ten
(+ 10). Component PI51 0 then connects J151
Q
then con-
nects J1510 pins 1 and 2. The signal to the base of Q1401,
in all cases, must be 1 MHz.
Emitter follower Q1401 and associated components op-
erate as a single-pole filter generating a sawtooth type sig-
nal at the negative input pin of comparator U1400. For the
TlME A
+
B, WIDTH A, and EVENTS B DUR A functions,
the base of Q1300 is set low via pin 7 of shift register U1200
(as shown on Diagram 3). In these functions, the Noise Gen-
erator (Diagram 5), U1410, is enabled by applying +5 volts
to the V , , input, pin 4. The output from U1410 (pin 3) will be
-
12 volts to +5 volts signal with a pseudo-random edge
distribution. This signal is then attenuated by resistor,
R1410 and applied to pin 2 (+) of U1400. Also, with these
functions, U1400 operates as a phase modulator circuit.
The output (pin 7) of U1400 is a 1 MHz signal that is phase
REV JUL
1983