Section 3 Theory Of Operation; Introduction - Tektronix DC5010 Instruction Manual

Section
3 D C
501 0
THEORY OF OPERATION
Introduction
Refer to the Block Diagram illustration located in the
foldout pages at the rear of this manual during the following
discussion.
Signal Conditioning and Amplifiers
The functional blocks for the Signal Conditioning and
Amplifiers (Channel A and Channel B) are essentially identi-
cal. Each channel amplifier circuit contains seven magnetic
latching relays, which control the input conditioning and
routing of the front-panel input signals. Six relays control
the ac or dc coupling modes, the 1 or 5 attenuation factors,
and the termination impedance. The seventh relay provides
for a Channel A and Channel B commoning function. The
data for these relays are sent from the microprocessor via
-_
data shifted through serial-to-parallel shift registers, in these
functional blocks.
The Channel A and Channel B amplifiers use matched
DMOS FET followers that buffer the input signal and trigger
'
level. The buffered signal and trigger level are combined and
amplified in a differential cascode integrated circuit (IC). This
IC also provides for switching the output into a low pass
filter or straight through at full bandwidth.
Schmitt Triggers
The amplified signal and trigger level are applied to the
inputs of the Schmitt trigger IC. The differential Schmitt out-
put is applied to transistors that select the triggered slope.
This circuit also provides the Shaped Out signals.
D/A9s, Relay Protect, and Arming
The 50 Q protect circuitry consists of two "windown com-
parators (Channel A and Channel B). These comparators
receive the protect sense levels from the Channel A or
Channel B inputs (relays) and operate within a
+
2 volts win-
dow sense level. If these voltage levels vary up or down
from this window, the comparators will send a protection
signal (50 Q protect) to the microprocessor. The micro-
processor automatically changes the input impedance to
1 Mil and protects the 50 Q circuitry.
The arming input is applied from the front panel or rear
interface. This circuit consists of a 1 TTL input load with
appropriate input protection and a Schmitt trigger circuit for
noise immunity. The output provides the arming signal
(ARM).
Main Gating
After the Schmitt trigger, the signals to be measured are
routed through the proper logic gates for the operating
mode selected. These gates are enabled (or disabled) via
latched data in a serial-to-parallel shift register located in
this functional block.
The counter has what is sometimes called a "ratio archi-
tecture". That is, events are always accumulated in one
count chain, called Accumulator A, and a time related or
Channel B event count is accumulated in another counter
chain, called Accumulator B. The microprocessor actually
controls the measurement interval, which is typically asyn-
chronous with the input signals. Thus, two flip flop synchro-
nizers are used to guarantee that the accumulators always
see a whole number of pulses of input signals (Q1112) or a
whole number of pulses (U11 IOC) from the internal time
base that is being counted.
%
This functional block contains triggering level control and
10-bit digital-to-analog converters (DIA converters) for
The arming input (ARM), from D/A's, RELAY PROTECT
Channel A and Channel B. The operational amplifiers driven
AND ARMING functional block, is applied to this block
from the D/A converter output, set both the offset and range
where it is logically ANDed with the measurement GATE
for the individual channels.
generated by the microprocessor.
REV OCT 1981