Tektronix DC5010 Instruction Manual page 243

Theory of Operation-DC SO 10
DETAILED CIRCUIT DESCRIPTION
SIGNAL CONDITIONING AND
AMPLIFIERS-DIAGRAM
@
NOTE
Since the Channel B Signal Conditioning and Amplifier
circuitry is essentially identical to the Channel A cir-
cuitry, this description discusses the theory of
opration for the Channel A circuits only.
The Channel A input signal is routed to two magnetic
latching relays. Relays K1612S (Channel A) and K1632S
(Channel B) provide a normal mode operation (separate
channels) or common mode operation (both channels). In
the common mode operation (Common Separate), Channel
B input becomes an open circuit. The common mode oper-
ation is used when making risetime and falltime measure-
ments. In this mode, with the input impedance set to 50 Q ,
the leadless chip component, R1611, in conjunction with the
50 Q (TERM) in each channel, becomes an internal power
splitter. Relays K1611 S and K1510S provide for 50 52 or
1 MQ (TERM) input impedance selection. Resistor R1511
provides the 50 Q termination. When in 50 Q input imped-
ance, relay K1610S selects either ac or dc coupling
-
(COUPL). In the dc coupling position, resistor R1612 dis-
charges the ac coupling capacitor, C1610. Component
R1512 is the isolate resistor for the 50 Q Protect A sense
line, which will be discussed later. Relay K1511 selects ei-
ther the X I or X5 attenuation (ATTEN), when in 50 Q
(TERM).
In the 1 MQ termination, selected by K1611S, relay
K1600 selects either ac or dc coupling (COUPL). In the dc
coupling position, resistor R1601 discharges the ac coupling
capacitor, C1601. If X5 attenuation is selected, the signal
enters the hybrid attenuator, AT1505. The component
C1504 is a compensation capacitor and R1504 is the 1 MQ
termination resistor. When attenuated, resistors R1506 and
R1507 provide damping for optimum ac performance.
Input signal protection is provided by diode network,
CRl512, CRl510, C R l 5 l l l CRl513, and resistor Rl5lO
and capacitor C1518.
A matched pair of DMOS field effect transistors (FET),
Q1410, provide buffering for both the input signal (at pin 8)
and the triggering level signal (at pin 4). These matched FET
devices cause a matched level shift from 0 volts to approxi-
mately -4.5 volts. Diodes CRl411, VRl412 and CRl410,
VR1413 will limit large (overdriving) signals and protect inte-
grated circuit (IC) U1311. In common mode operation, differ-
ential transformer, TI410 converts a single-ended signal
into a differential signal at high frequencies. This helps to
provide for better high frequency performance and helps to
reject noise. The FET source followers each have a current
source. Transistor Q1402 is the current source for the trig-
gering level source follower output. Transistor Q1403 is the
current source for the input signal source follower output.
The IC U1311 is a cascode differential amplifier with
switched signal output capability. Signals can be either
passed straight through at full bandwidth or through a two-
pole low pass filter that passes frequencies from dc to ap-
proximately 20 MHz. These signals are switched by control
voltages generated from the logic signal
at pins 12
and 11 of U 1 3 l l . Being complimentary, through Q1211 (sig-
nal inverter) and (2121 0 (buffer) they appear in the Channel
B circuitry as well. Therefore, the filters may or may not be
selected by these inputs.
Resistor R1417 sets the gain for U1311 (pins 2 and 3).
This leadless chip component is soldered directly to the IC
pins for optimum ac performance. Transistors Q1400 and
Q1401 are current sources for the cascode differential input.
Low frequency peaking is provided by components R1406,
R1405, and C1403.
SCHMITT TRIGGERS-DIAGRAM
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The buffered and amplified differential signal is applied to
pins 2 and 3 of U1310 (Schmitt Trigger circuit). These sig-
nals are looped through this IC and appear at pins 12 and
1 1, with the load resistors R1313 and R1216. Transistor
Q1303 is a current source for the Schmitt Trigger latch de-
vices. The Schmitt Trigger differential output (pins 6 and 8 of
U1310) is level shifted by transistors Q1204, Q1302,
Q1300, and Q1301. Positive slopes are selected by Q1204
and Q1302 and negative slopes are selected by Q1300 and
Q1301. These common base stage level shifters are driven
by the
+
SLOPE A and
-
SLOPE A signals through tran-
sistors Q1202, Q1201, and associated circuitry. The shaped
output signal from Q1204 or Q1300 enters Q1203 base,
inverts and outputs to J1201 (CH A SHAPED OUT). The
output signal (CH A ECL) from (21302 or Q1301 routes to
the ECL logic circuitry (Diagram 3). An operational amplifier,
U1202B (Diagram 2) sets the mean dc level of the ECL sig-
nal to the correct value. A threshold level generated by an
ECL signal (Diagram 3) is sensed at pin 5, U1202B and
compared to the mean level sensed at pin 6, U1202B. The
output (pin 7, U1202B) supplies the current necessary to
adjust the level shifted output to the correct mean ECL
threshold level.
REV DEC 1982