Philips DVDR985 Technical Training Manual page 114

DV_HS_IN
DV_HS_OUT
DV_IN_CLK
DV_IN_DATA (7:0)
DV_IN_HS
DV_IN_VS
DV_LCN
DV_PDN
DV_RSTN
DV_RWN
DV_VS
EFM
EMI_A (21:1)
EMI_BE0N
EMI_BE1N
EMI_CAS0N
EMI_CE1N
EMI_CE2N
EMI_CE3N
EMI_D (15:0)
EMI_PROCCLK
EMI_RWN
Decoder)EMI_WAIT
EMPRESS_BOOT
EMPRESS_IRQN
FDS
FIFO
FIFOA_A (0:15)
FIFOA_OEN
FIFOA_WEN
FLASH_OEN
FPGA
FTC
G_IN_VIP
G_OUT
G_OUT_B
GNDD
HD_M_AD (13:0)
HD_M_CASN
HD_M_CLK
HD_M_CS0N
HD_M_DQ (15:0)
HD_M_DQML
HD_M_DQMU
HD_M_RASN
HD_M_WEN
HF
HSOUT
I 2 C
DVCODEC Horizontal synchronization In
DVCODEC Horizontal synchronization Out
Digital Video in Clock from DVIO Board
Digital Video in Data bus from DVIO Board
Digital Video in horizontal synchronization from DVIO Board
Digital Video in vertical synchronization from DVIO Board
DVCODEC Last Code Interrupt
DVCODEC Power Down
DVCODEC System Reset for NW701
DVCODEC Read/Write control signal
DVCODEC Vertical synchronization
Eight to Fourteen bit Modulation
External Memory Interface Address Bus (Host Decoder)
External Memory Interface Lower byte Enable (Host Decoder)
External Memory Interface Upper byte Enable (Host Decoder)
External Memory Interface SDRAM column Address strobe
External Memory Interface VSM Lower bank Enable
External Memory Interface VSM Higher bank Enable
External Memory Interface flash IC's Enable
External Memory Interface Data Bus (Host Decoder)
External Memory Interface Processor Clock (Host Decoder)
External Memory Interface Read/Write control signal (Host
External Memory Interface Wait state request (Host Decoder)
EMPRESS BOOT select Input
EMPRESS Interrupt request Output
Full Diagnostic Software
First In First Out memory
FIFO buffer A Address bus
FIFO buffer A Output Enable
FIFO buffer A Write Enable
FLASH Output Enable control signal
Field Programmable Gate Array
Fast Track Count
Video green Input to Video Input Processor
Video green Output from Host Decoder
Filtered green Video Output from Host Decoder
Digital Ground
Host Decoder SDRAM Address bus
Host Decoder SDRAM column Address strobe
Host Decoder SDRAM Clock
Host Decoder SDRAM chip select
Host Decoder SDRAM Data bus
Host Decoder SDRAM Data mask Enable (Lower)
Host Decoder SDRAM Data mask Enable (Upper)
Host Decoder SDRAM row Address strobe
Host Decoder SDRAM write Enable
High Frequency/signal from the disc
Horizontal synchronization OUT
I 2 C/serial communication protocol
105