Philips DVDR985 Technical Training Manual page 112

AE_DATAO
AE_WCLK
AE_WCLK_DV
AE_WCLK_VSM
ANA_WE
ANA_WE_LV
AUD_BCLK
AUD_MUTE
AUD_SDI
AUD_SDO_CON
AUD_SDO_DAC
AUD_WS_701
AUD_WS_OUT
AWSOME
B_IN_VIP
B_OUT
B_OUT_B
BA
BCLK_CTL_SERVICE
BE_BCLK
BE_BCLK_VSM
BE_CPR
BE_DATA_RD
BE_DATA_WR
BE_FAN
BE_FLAG
BE_IRQN
BE_LOADN
BE_RXD
BE_SUR
BE_SYNC
BE_TXD
BE_V4
BE_WCLK
BE
BUFENN_AUD
BUFENN_VID
C_IN
C_IN_VIP
C_OUT
C_OUT_B
CALF
CAS
CAV
CB_OUT (9:0)
CCLK
CLK4
Audio Encoder Output Data (PCM)
Audio Encoder I 2 S word Clock
Audio Encoder I 2 S word Clock to DVIO
Audio Encoder I 2 S word Clock to VSM
Analog write Enable Decoder
Analog write Enable Low Voltage
Audio Bit Clock
Audio Mute
Audio Serial Data Input
Audio Serial Data Output to buffer IC 7505
Audio Serial Data Output to DAC IC 7506
Audio Word Select to DV CODEC IC 7404
Audio Word Select to buffer IC 7505
Adip decoding Wobble processing Error correction Synchronous
start/stop and Occasionally Mend Errors
Video blue Input to Video Input Processor
Video blue Output from Host
Filtered blue Video Output
Bank Address
Bitclock control Service Interface
Basic Engine I 2 S bit Clock
Basic Engine I 2 S bit Clock to VSM
Basic Engine Control Processor ready to accept Data
Basic Engine Data read
Basic Engine Data write
Basic Engine FAN
Basic Engine error flag
Basic Engine interrupt request
Basic Engine LOAD (LOW active)
Basic Engine S2B received Data
Basic Engine Servo Unit Ready to accept Data (S2B)
Basic Engine sector/abs time Sync
Basic Engine S2B transmitted Data
Basic Engine versatile Input pin
Basic Engine I 2 S word Clock
Basic Engine/Mechanism-Servo Board
Buffer Enable Audio
Buffer Enable Video
Video Chrominance Input
Chrominance Input to Video Input Processor
Chrominance Output from Host Decoder
Filtered Chrominance Output
Laser Calibration Final voltage
Column Address strobe
Constant Angular Velocity
Chrominance Blue out
Configuration Clock
SDRAM Clock
103