Philips DVDR985 Technical Training Manual page 115

I 2 S
INITN
IO (0:30)
ION
IRESET_DIG
ISPN
JTAG3_TCK
JTAG3_TD_VIP_TO_VE
JTAG3_TD_VSM_TO_VIP JTAG Transmitted Data Versatile Stream Manager to Video Input
JTAG3_TMS
JTAG3_TRSTN
LADIC
LCASN
LDON
LINK_AVCLKLINK IC
LINK_AVFSYNC
LINK_AVREADY
LINK_AVSYNC
LINK_AVVALID
LINK_CSN
LINK_INTN
LINKFIFO_DQ (0:7)
LLD
LLP
LOAD_DVN
LPCM
LRCLK
MACE
Mpeg
MUTEN
MUTEN_LV
NVM
OPC
ORD
OPU
P_SCAN_YUV (7:0)
PA (0:15)
PCS
PCM
PPN
PPNO
PWRN
SYSCLK_VSM_5508
PAD (0:7)
PALE
PHY_CAN
PHY_LPS
PINT0N
Integrated IC Sound Buss (3.3V High)
Initiate Configuration
Data bus of IC7404
Inverted ON: Enable the power Supply for the Digital Board when LOW
Initialization of the Digital Board, HIGH when power ON
In System Program Line (used for programming IC7203)
JTAG Test Clock
JTAG Transmitted Data Video Input Processor to Video Encoder
Processor
JTAG Test Mode Select
JTAG Test part ResetN
LAser Drive IC
Lower Column Address strobe for IC7404 DRAMS
Laser Drive On
Audio/Video Interface Clock
LINK IC Audio/Video frame Sync
LINK IC Audio/Video Data ready to send
LINK IC Audio/Video packet Sync
LINK IC Audio/Video Data valid
LINK IC chip select
LINK IC interrupt
Audio Video Data interface
Loss Less Decoder
Laser Low Power
LOAD Digital Video (LOW active)
Linear Pulse Code Modulation
Left/Right Clock
Mini All CD Engine
Motion Picture Experts Group (compression scheme)
Mute Enable
Mute Enable Low Voltage
Non Volatile Memory
Optimum Power Cailibration
Radial Drive disable
Optical Pickup Unit
Progressive Scan Digital Video bus
SRAM processor Address
Position Control Sled
Pulse Code Modulation
Wobble Pre-Processor signal
Wobble Pre-Processor signal Output signal
Processor write
System Clock VSM and Host decoder
SRAM processor Data
Processor Address Latch Enable
PHY 1394 cable not active
LINK IC power status
Processor interrupt 0
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