Pioneer PDP-6071PU Service Manual page 217

5
Pin Function
Pin Type Mnemonic
Inputs R
AIN
G
AIN
B
AIN
HSYNC
VSYNC
SOGIN
CLAMP
COAST
Outputs Red [7:0]
Green [7:0]
Blue [7:0]
DATACK
HSOUT
VSOUT
SOGOUT
References REF BYPASS Internal Reference Bypass
MIDSCV
FILT
Power Supply V
D
V
DD
PV
D
GND
Control SDA
SCL
A0
5
6
Function
Analog Input for Converter R
Analog Input for Converter G
Analog Input for Converter B
Horizontal SYNC Input
Vertical SYNC Input
Input for Sync-on-Green
Clamp Input (External CLAMP Signal)
PLL COAST Signal Input
Outputs of Converter Red, Bit 7 is the MSB 3.3 V CMOS
Outputs of Converter Green, Bit 7 is the BSB 3.3 V CMOS
Outputs of Converter Blue, Bit 7 is the BSB 3.3 V CMOS
Data Output Clock
HSYNC Output (Phase-Aligned with DATACK) 3.3 V CMOS
VSYNC Output (Phase-Aligned with DATACK) 3.3 V CMOS
Sync-on-Green Slicer Output
Internal Midscale Voltage Bypass
Connection for External Filter Components
for Internal PLL
Analog Power Supply
Output Power Supply
PLL Power Supply
Ground
Serial Port Data I/O
Serial Port Data Clock (100 kHz Maximum) 3.3 V CMOS
Serial Port Address Input 1
PDP-6071PU
6
7
Value Pin No.
0.0 V to 1.0V 54
0.0 V to 1.0V 48
0.0 V to 1.0V 43
3.3 V CMOS 30
3.3 V CMOS 31
0.0 V to 1.0 V 49
3.3 V CMOS 38
3.3 V CMOS 29
70–77
2–9
12–19
3.3 V CMOS 67
66
64
3.3 V CMOS 65
1.25 V 58
37
33
3.3 V 39, 42, 45, 46, 51, 52, 59, 62
3.3 V 11, 22, 23, 69, 78, 79
3.3 V 26, 27, 34, 35
0 V 1, 10, 20, 21, 24, 25, 28, 32, 36, 40,
41, 44, 47, 50, 53, 60, 61, 63, 68, 80
3.3 V CMOS 57
56
3.3 V CMOS 55
7
8
A
B
C
D
E
F
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