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H-LCD2000Service Manual
Chassis Description
AD9883A
The
AD9883A
is a c
capturing RGB graphics signals from
encode rate c
a
pability
280 ×
up to SXGA (1
The
AD9883A's on-chip PLL generates a pixel clock from HSYNC and COAST inputs.
Pixel clock ou put fr
t
equencies range from 20 MHz to 140 MHz.
Features
140 MSPS Maximum Conversion Rate
300 MHz Analog Bandwidth
0.5 V to 1.0 V Analog In
500ps p-p PLL Clock Jitter at 110 MSPS
Low Power Supply
Full Sync Processing
Sync Detect for "Hot Plugging"
Midscale Clamping
Power
-Down Mode
Low Power: 500 mW Typical
4:2:2 Output Format Mode
AD9883A
Pin Function
Pin
Name
70～
77
RED0～RED7
GREEN0
2～9
GREEN7
12～19
BLUE0～BLUE7
67
DATACK
66
HSOUT
65
SOGOUT
64
VSOUT
37
MIDSCV
58
REF
BYP
31
VSYNC
30
HSYNC
43
BAIN
49
SOGIN
48
GAIN
54
RAIN
29
COAST
38
CLAMP
55
A0
56
SCL
omplete 8-bit,
140 MSPS m
personal computers and workstations. Its 140 MSPS
and full powe
r analog bandwidth of
1024 at 75 Hz).
put Range
Function
Outputs of Converter "Red," Bit 7 is the MSB
～
Outputs of Converter "Green Bit 7 is the MSB
Outputs of Converter "Blue," Bit 7 is the MSB
Data Output Clock
HSYNC Output (Phase-Aligned with DATACK)
Sync on Green Slicer Output
VSYNC Output (Phase-Aligned with DATACK)
Internal Midscale Voltage Bypass
Internal Reference Bypass
Vertical SYNC Input
Horizontal SYNC Input
Analog Input for Converter B
Input for Sync-on-Green
Analog Input for Converter G
Analog Input for Converter R
PLL COAST Signal Input
Clamp Input (External CLAMP Signal)
Serial Port Address Input 1
Serial Port Data Clock (100 kHz Maximum)
57
onolithic analog interface optimized for
300 MHz supports resolutions
20
Page 20 of
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