Philips BJ2.4U Service Manual page 133

Circuit Descriptions, Abbreviation List, and IC Data Sheets
9.8 PNX2015: AVIP
9.8.1 Introduction
The AVIP (Audio Video Input Processor) receives the digital
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data via the I D link (coming from MPIF). It reformats this data
and maps (synchronizes) the data to the clock of the AVIP.
Then a digital AGC is passed. After this, the video decoding is
performed in the VIDDEC-block of the AVIP. The decoded
video is sent to an output block, which formats the data to an
ITU-656 compatible standard data stream.
The AVIP power supply is 1.2 V and 3.3 V. To ensure
synchronization of video streams processed across the VIPER
and PNX2015 devices, a 27 MHz is coming from the VIPER.
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The AVIP is I C driven.
Initialization of this IC begins with a hard reset (MIPS-RESET)
provided by the VIPER. Besides video decoding, the AVIP is
also used for decoding and presentation of all audio output
streams in the system.
9.8.2 Block Diagrams
Below the main functions and features in the AVIP for video
and audio are given.
I2D1
CVBS/YC/YUV
VIDDEC
I2D2
I2D
DCU
I2D3
SIF or L/R
DemDec
GP
I2Sout
Figure 9-18 AVIP block diagram
Main AVIP function:
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• I D receiver.
• Color decoding into ITU-601 compatible format (1fH/2fH).
• Interface with 3D comb filter (called Columbus in this
chassis).
• VBI data capture via DCU (Teletext, CC, etc.).
• ITU-656 formatting.
• Audio demodulation and decoding via DEMDEC.
• Audio processing and D/A conversion.
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I D Receiver
I2D transmitter I2D AVIP
CVBS pri /YC/
Y yuv
I2D I2D
transmitter receiver
L1/R1
YUV/ UV yuv
I2D I2D
transmitter receiver
L2/R2
CVBS sec
I2D I2D
transmitter receiver
SIF
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Figure 9-19 I D receiver block diagram
Cvbs_yyc
ITU-656
ITU-656
VBI bytes
L
Audio
Processing
R
I2SIn
E_14700_069.eps
CVBS pri /Y yc
Y yuv / C yc
UV yuv
VAL1
CVBS sec
VAL
VAL2
L1/R1
VAL3
L2/R2
SIF
E_14700_070.eps
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The receiver block gets the serial data stream and converts it
to a parallel stream. This parallel data is fed to the "de-
multiplexer and formatter " block where the selected audio/
video stream is forwarded to the video and audio decoder for
further processing. This communication bus is completely
digital and very difficult to monitor.
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The I D link has the following characteristics.
• The data-link runs at 297 MHz / 594 Mbps.
• The driver rise/fall time is around 200 ps.
• The data-link uses differential signals.
VIDDEC (Video Decoder)
Video Decoder
CVBS/Yyc
Yuv/Cyc
Uyuv
Vyuv
FBL1/Hsync1
FBL2/Hsync2
Vsync1
Vsync2
Figure 9-20 VIDDEC block diagram
The CVBS/YC/YUV signals (coming from the I
block) enter the DMSD block (Digital Multi Standard Decoder)
via the AGC (Automatic Gain Control) block. The multiplexer
block (MUX) takes care of the correct output signal. The sync
signals are processed in the sync block.
The VIDDEC has the following main functions:
• Multi standard color decoder.
• Automatic system recognition.
• Fully programmable static or automatic (AGC) for all
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analog video base band signals.
• AGC on sync amplitude in digital domain.
• Selectable peak white control.
• AGC for chrominance (PAL and NTSC only).
• Programmable Luminance and Chrominance bandwidth
for CVBS and Y/C sources.
• Programmable clamp window for the selected video base
band signals.
• Digital PLL for synchronization on 2fH and ATSC
standards.
• Horizontal (including 3-level sync for 2fH) and vertical sync
detection.
• Automatic detection of 50/60Hz ATSC field frequency.
• Adaptive 2/4-line delay comb filter for two-dimensional
Chrominance/Luminance separation.
• Copy protected source detection according to MacroVision
up to version 7.01
• Possibility of RGB insertion through fast blanking in CVBS
input mode, not in Y/C.
BJ2.4U/BJ2.5U PA
Yyc
YUV
Digital Multi
Standard Decoder
Cyc (DMSD)
AGC
Yuv
Uyuv
Vyuv
FBL1
Sync
sync
FBL2
9. EN 133
mux
YUV
(Fast blank)
HVsync
E_14700_071.eps
021104
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D receiver