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STR-DA6400ES
QQ
3 7 63 1515 0
D VIDEO BOARD IC3606 FLI8638-LF (VIDEO PROCESSOR2)
Pin No.
Pin Name
A1
NC
A2
MSTR1_SDA
A3
MSTR1_SCL
A4, A5
FSDATA1, FSDATA3
A6
FSDQM0
FSDATA5, FSDATA7,
A7 to A10
FSDATA9, FSDATA11
A11
FSDQM1
FSDATA13,
A12, A13
FSDATA15
A14
VDDA18_DLL
FSDATA17,
A15, A16
FSDATA19
A17
FSDQS2
FSDATA21, FSDATA23,
A18 to A21
FSDATA25, FSDATA27
A22
FSDQS3
A23, A24
FSDATA29, FSDATA31
A25, A26
RPLL_AGND
B1
BDATA0
B2
OCM_UDO_1
B3
OCM_UDI_1
B4, B5
FSDATA0, FSDATA2
B6
FSDQS0
FSDATA4, FSDATA6,
B7 to B10
FSDATA8, FSDATA10
TE
L 13942296513
B11
FSDQS1
B12, B13
FSDATA12, FSDATA14
B14
VSSA18_DLL
B15, B16
FSDATA16, FSDATA18
B17
FSDQM2
FSDATA20, FSDATA22,
B18 to B21
FSDATA24, FSDATA26
B22
FSDQM3
B23, B24
FSDATA28, FSDATA30
B25
RPLL_DGND
B26
XTAL
C1 to C3
BDATA3 to BDATA1
C4
FSCKE
C5
FSCLKN
C6 to C8
FSADDR8 to FSADDR6
C9
FSVREF
FSADDR5, FSADDR12,
C10 to
FSADDR9, FSADDR4,
C18
FSADDR11, FSADDR3
to FSADDR0
C19
FSVREF
C20, C21
FSBKSEL1, FSBKSEL0
C22
FSCS1
C23
FSWE
C24
FSRAS
www
C25
RPLL_1.8V
C26
TCLK
D1 to D3
BDATA6to BDATA4
.
D4
DDR_2.5V
D5
FSCLKP
D6 to D8
DDR_2.5V
178
http://www.xiaoyu163.com
I/O
-
Not used
O
Power detection signal output to the video system controller
O
Busy signal output to the video system controller
I/O
Two-way data bus with the SD-RAM
O
Data mask signal output to the SD-RAM (upper byte)
I/O
Two-way data bus with the SD-RAM
O
Data mask signal output to the SD-RAM (lower byte)
I/O
Two-way data bus with the SD-RAM
-
Power supply terminal (+1.8V)
I/O
Two-way data bus with the SD-RAM
O
Data strobe signal output to the SD-RAM (upper byte)
I/O
Two-way data bus with the SD-RAM
O
Data strobe signal output to the SD-RAM (lower byte)
I/O
Two-way data bus with the SD-RAM
-
Ground terminal
I
Digital video signal input terminal
O
Serial data output to the video system controller
I
Serial data input from the video system controller
I/O
Two-way data bus with the SD-RAM
O
Data strobe signal output to the SD-RAM (upper byte)
I/O
Two-way data bus with the SD-RAM
O
Data strobe signal output to the SD-RAM (lower byte)
I/O
Two-way data bus with the SD-RAM
-
Ground terminal
I/O
Two-way data bus with the SD-RAM
O
Data mask signal output to the SD-RAM (upper byte)
I/O
Two-way data bus with the SD-RAM
O
Data mask signal output to the SD-RAM (lower byte)
I/O
Two-way data bus with the SD-RAM
-
Ground terminal
O
System clock output terminal
I
Digital video signal input terminal
O
Clock enable signal output to the SD-RAM
O
Clock signal (negative) output to the SD-RAM
O
Address signal output to the SD-RAM
O
Reference voltage output to the SD-RAM
O
Address signal output to the SD-RAM
O
Reference voltage output to the SD-RAM
O
Bank select signal output to the SD-RAM
O
Chip select signal output terminal
O
Write enable signal output to the SD-RAM
O
Row address strobe signal output to the SD-RAM
-
Power supply terminal (+1.8V)
I
System clock input terminal (19.6608 MHz)
x
ao
u163
y
I
Digital video signal input terminal
i
-
Power supply terminal (+2.5V)
O
Clock signal (positive) output to the SD-RAM
-
Power supply terminal (+2.5V)
http://www.xiaoyu163.com
2 9
8
Description
Not used
Q Q
3
6 7
1 3
1 5
Not used
Not used
Not used
co
Not used
.
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9

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