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DSP BOARD IC5202 ADSST-AVR-1131 (DSP2)
Pin No.
Pin Name
A1
CLKCFG0
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13, A14
B1
CLKCFG1
B2
B3
B4
B5
B6
B7
B8
B9
TE
L 13942296513
B10
B11
B12 to B14
BOOTCFG1,
C1, C2
BOOTCFG0
C3, C12,
C13
C14, D1
D2,
D4 to D6,
D9 to D11,
D13
D14, E1
E2,
E4 to E6,
E9 to E11,
E13
E14
SF2_DSP2_CE
F1
F2
F4 to F6,
F9 to F11
F13
P_ERROR
F14
G1
G2
G13
www
G14
H1
.
H2
H13
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I/O
I
Clock frequency setting terminal
XTAL
O
System clock output terminal (25 MHz)
TMS
I
Mode selection signal input terminal (for JTAG)
TCK
I
Clock signal input terminal (for JTAG)
TDI
I
Data input terminal (for JTAG)
CLKOUT
O
Clock signal output terminal
TDO
O
Data output terminal (for JTAG)
EMU
-
Not used
When DSP2 is master: Serial data output to the serial fl ash
MOSI
I/O
When DSP2 is slave: Serial data input from the DSP controller
When DSP2 is master: Serial data input from the serial fl ash
MISO
I/O
When DSP2 is slave: Serial data output to the DSP controller
SPIDS
I
Serial data latch pulse signal input from the DSP controller
VDDINT
-
Power supply terminal (+1.2V)
GND
-
Ground terminal
I
Clock frequency setting terminal
GND
-
Ground terminal
VDDEXT
-
Power supply terminal (+3.3V)
CLKIN
I
System clock input terminal (25 MHz)
TRST
I
Reset signal input terminal (for JTAG)
AVSS
-
Ground terminal
AVDD
-
Power supply terminal (+1.2V)
VDDEXT
-
Power supply terminal (+3.3V)
When DSP2 is master: Serial data transfer clock signal input from the DSP controller
SPICLK
I/O
When DSP2 is slave: Serial data transfer clock signal output to the serial fl ash
RESET
I
Reset signal input from the DSP controller
VDDINT
-
Power supply terminal (+1.2V)
GND
-
Ground terminal
I
Boot mode setting signal input from the DSP controller
GND
-
Ground terminal
VDDINT
-
Power supply terminal (+1.2V)
GND
-
Ground terminal
VDDINT
-
Power supply terminal (+1.2V)
GND
-
Ground terminal
O
Chip enable signal output to the serial fl ash
FLAG1
I
Audio muting control signal input from the digital audio interface receiver or HDMI receiver
FLAG0
O
Interrupt request signal output to the DSP controller
GND
-
Ground terminal
I
PLL lock error signal and data error fl ag input from the DSP1
DPFSCK
I
Master clock signal input from the digital audio interface receiver or HDMI receiver
AD7
I/O
Two-way data bus with S-RAM and address signal output to the address latch
VDDINT
-
Power supply terminal (+1.2V)
VDDEXT
-
Power supply terminal (+3.3V)
Bit clock signal input for PCM audio signal input from the digital audio interface receiver,
DPBCK
I
DSP1 or HDMI receive
x
ao
y
AD6
I/O
Two-way data bus with S-RAM and address signal output to the address latch
i
VDDEXT
-
Power supply terminal (+3.3V)
L/R sampling clock signal input for PCM audio signal input from the digital audio interface
DPLRCK
I
receiver, DSP1 or HDMI receiver
http://www.xiaoyu163.com
8
Not used
Not used
Not used
Not used
Not used
Q Q
3
6 7
1 3
u163
.
STR-DA6400ES
2 9
9 4
2 8
Description
Not used
1 5
0 5
8
2 9
9 4
"L": reset
m
co
9 9
2 8
9 9
153

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