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STR-DA6400ES
QQ
3 7 63 1515 0
D VIDEO BOARD IC3604 YGV629-VZ (OSD CONTROLLER)
Pin No.
Pin Name
1
PLLVDD
2
FILTER
3
PLLVSS
4
NC
5 to 10
PLLCTL5 to PLLCTL0
11
DTCKS_N
12
DTCK_IN
13
VSS
14
VDD
15 to 22
D0 to D7
23
WAIT_N
24
READY_N
25
INT_N
26
VDD
27
VSS
28
CS_N
29
WR_N
30
RD_N
31 to 33
PS2 to PS0
34
SDOUT
35
SDIN
36
SCS_N
37
SCLK
38
SER_N
TE
L 13942296513
39
RESET_N
40
VSS
41
VDD
42
MA0
43 to 47
MA1 to MA5
48
VSS
49 to 54
MA6 to MA11
55
VDD
56
VSS
57 to 62
MA12 to MA17
63
VSS
64 to 70
MA18 to MA24
71
VDD
72
VSS
73
MWE_N
74
MOE_N
MD15, MD7, MD14,
75 to 80
MD6, MD13, MD5
81
VSS
82
VDD
MD12, MD4, MD11,
83 to 90
MD3, MD10, MD2,
MD9, MD1
91
VSS
92
VDD
www
93, 94
MD8, MD0
95
RAHZ_N
96 to 98
XTEST2 to XTEST0
99
VSIN_N
.
100
HSIN_N
101
NC
176
http://www.xiaoyu163.com
I/O
-
Power supply terminal (+3.3V)
I
Filter connection terminal for internal PLL
-
Ground terminal
-
Not used
I
PLL setting terminal
I
Clock signal input terminal
I
Clock signal input terminal
-
Ground terminal
-
Power supply terminal (+3.3V)
I/O
Two-way data bus with the video system controller and S-RAM
O
Wait signal output to the video system controller
O
Ready signal output terminal
O
Interrupt signal output to the video system controller
-
Power supply terminal (+3.3V)
-
Ground terminal
I
Chip enable signal input from the video system controller
I
Write enable signal input from the video system controller
I
Read enable signal input from the video system controller
I
Address signal input from the video system controller
O
Serial data output terminal
I
Serial data input terminal
I
Chip select signal input terminal
I
Serial data transfer clock signal input terminal
I
CPU interface selection setting terminal
I
Reset signal input from the video system controller
-
Ground terminal
-
Power supply terminal (+3.3V)
O
Address signal output terminal
O
Address signal output to the fl ash memory
-
Ground terminal
O
Address signal output to the fl ash memory
-
Power supply terminal (+3.3V)
-
Ground terminal
O
Address signal output to the fl ash memory
-
Ground terminal
O
Address signal output to the fl ash memory
-
Power supply terminal (+3.3V)
-
Ground terminal
O
Write enable signal output to the fl ash memory
O
Output enable signal output to the fl ash memory
I/O
Two-way data bus with the fl ash memory
-
Ground terminal
-
Power supply terminal (+3.3V)
I/O
Two-way data bus with the fl ash memory
-
Ground terminal
-
Power supply terminal (+3.3V)
I/O
Two-way data bus with the fl ash memory
-
Not used
x
ao
u163
y
-
Not used
I
i
Vertical sync signal input terminal
I
Horizontal sync signal input terminal
-
Not used
http://www.xiaoyu163.com
2 9
8
Description
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Fixed at "H" in this set
Q Q
3
6 7
1 3
1 5
"L": reset
Not used
co
Not used
.
Not used
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9

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