Lippert PC/104-Plus Technical Manual page 22

Technical Manual PC/104-Plus "Cool RoadRunner II" Version 1.16
reload the stored value and reset the watchdog timer time-out status bit if set. If all three
system events are disabled the watchdog timer will inevitably time out.
The watchdog timer may be configured to generate an interrupt on the rising edge of the
time-out status bit. The watchdog timer interrupt is mapped to an interrupt channel through
a configuration register. When mapped to an interrupt the interrupt request pin reflects the
value of the watchdog timer time-out status bit.
The used registers of the Super-I/O are shown in the following table:
Index-register
0x07
0xf1
(default = 00)
0xf1
0xf2
(default = 00)
0xf2
...
0xf2
0xf3
(default = 00)
0xf3
0xf3
0xf3
0xf3
0xf3
0xf3
0xf3
0xf3
0xf3
0xf3
0xf3
...
0xf3
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Data
0x08
0x00
0x80
0x00
0x01
...
0xff
Bit [0] = 0
Bit [0] = 1
Bit [1] = 0
Bit [1] = 1
Bit [2] = 0
Bit [2] = 1
bit [3] = reserved
bit [7..4] = 0
bit [7..4] = 1
bit [7..4] = 2
bit [7..4] = 3
bit [7..4] = 4
...
bit [7..4] = f
April 2004
Action
select functional
group 08
timer unit in minutes
timer unit in seconds
time-out disabled
time-out = 1 min/sec
...
time-out = 255
min/sec
WDT is not affected
upon I/O read/write
of I/O port 0x201
WDT is reset upon
I/O read/write of I/O
port 0x201
WDT is not affected
by keyboard
interrupts
WDT is reset upon a
keyboard interrupt
WDT is not affected
by mouse interrupts
WDT is reset upon a
mouse interrupt
------------------
WDT interrupt
mapping disable
WDT interrupt
mapping to IRQ 1
Invalid
WDT interrupt
mapping to IRQ 3
WDT interrupt
mapping to IRQ 4
...
WDT interrupt
mapping to IRQ 15
Page 22 of 42
Program
SMCW 07 08
SMCW f1 00
SMCW f1 80
SMCW f2 00
SMCW f2 01
...
SMCW f2 ff
SMCW f3 x0
SMCW f3 x1
SMCW f3 x0
SMCW f3 x2
SMCW f3 x0
SMCW f3 x4
------------------
SMCW f3 0x
SMCW f3 1x
------------------
SMCW f3 3x
SMCW f3 4x
...
SMCW f3 fx