Watchdog; Short-Time Watchdog Timer; Long-Time Watchdog Timer - Lippert PC/104-Plus Technical Manual

Technical Manual PC/104-Plus "Cool RoadRunner II" Version 1.16
The signals of the Ethernet interface are located on the IDC10 header "Ethernet". An
adapter cable from IDC10 to RJ45 connector is available.

1.26 Watchdog

The board has two different independent watchdog systems, which are programmed
through the Super I/O.

1.26.1 Short-time watchdog timer

A short-time watchdog is realized with a Maxim 691 Reset/Watchdog circuit. The trigger
time of this watchdog is 400ms and accessible by the Super I/O controller through the
functional group 8. To activate the short-time watchdog the contents of the register '0xE2'
has to be set to '00'. To trigger this watchdog the contents of the register '0xE2' has to be
changed within 400ms from '00' to '02' or back from '02' to '00'. If there is no change of the
register within 400ms the watchdog releases and generates a full hardware reset.
Program example:
The status of the watchdog can be read through the register F6, Bit1 (Bit0 and Bit2-Bit7
are don't care) of the Super I/O. A low level at this pin indicates that a watchdog time-out
has occurred.

1.26.2 Long-time watchdog timer

A long-time watchdog timer is implemented in the Super I/O. The watchdog time-out status
bit may be mapped to an interrupt. It can also brought out as hardware reset. Both options
have to be programmed to the corresponding configuration registers of the Super I/O.
This watchdog timer has a time-out ranging from either 1 to 255 minutes with one-minute
resolution or 1 to 255 seconds with one-second resolution. As soon as the watchdog timer
is activated it starts counting down from the value loaded. When the count value reaches
zero the counter stops and sets the watchdog time-out status bit. Regardless of the current
state of the watchdog timer, the time-out status bit can be directly set or cleared by the
host CPU.
There are three system events that can reset the watchdog timer. These are a keyboard
interrupt, a mouse interrupt or I/O reads/writes to address 0x201. The effect on the watch-
dog timer for each of these system events may be individually enabled or disabled. When
a system event is enabled the occurrence of this event will cause the watchdog timer to
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SMCW 07 08
SMCW E2 00
SMCW E2 02
SMCW E2 00
...
...
...
SMCW E2 02
SMCW E2 00
...
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