LG 77EG9700 Service Manual page 85

URSA9 Block Diagram
Flash(4MB)
4K@60p Vx1 8 Lane Video
U14
1080p / 2160p Vx1 4 Lane OSD
URSA9_CONNECT
[GPIO[3]]
Vx1_LOCKn_O/V
[LOCKN_D/Q]
I2CS_SDA/SCL
(URSA Debug)
[SPI4_DI/DIM9/GPIO53]
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
SPI_CZ
SPI_D
O
SPI_CK
Serial SPI_DI
GPIO[25]
FLASH_WP_URSA
16x4
DDR3
1Gb x 4 (1600)
[Tx_U14_0N/0P~7N/7P]
[Tx_U14_8N/8P~11N/11P]
[GPIO[15]]
[GPIO[16]/[17]]
[I2CS_SDA/SCL]
UART2_RX
GPIO[1]/[0]
UART2_TX
XIN_URSA
URSA9
XO_URSA
LGE7410
[TXDBN0/P0~N7/P7_L]
[TXDAN0/P0~N7/P7_L]
Data_Format_0/1
[GPIO[4/5]]
3D_EN
[SPI4_CK/DIM8/GPIO52]
TCON_I2C_EN
[INT_R21/GPIO[41]]
L_DIM_EN
[SPI4_DI/DIM9/GPIO53]
LOCKn_IN/ HTPDn_IN
[VX1T_LOCKN]
[VX1T_HTDPN]
URSA_RESET_SOC
[RESET]
(H13D GPIO[26])
DIM5/GPIO[37]
DIM6/GPIO[38]
DIM7/GPIO[39]
X-tal
24MHz
Vx1 8Lane(12Lane_5K) 41P
Vx1 8Lane 51P
BIT[2/1/0]
URSA_BIT0/1/2
0/0/0 4K@120P _16Lanes
0/0/1
0/1/0 5K@120P _ 20Lanes
Panel
3840x2160@120
p
H1
I2C_SCL1/SDA1
3
UD_V x 1 Lane
4K@60P _ 8Lanes
LGE Internal Use Only