LG 77EG9700 Service Manual page 63
Chassis: ea41c
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Also See for 77EG9700:
- Owner's manual (56 pages) ,
- Operating manual (53 pages) ,
- Owner's manual (44 pages)
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URSA9_NON_D9
IC2500
LGE7411(URSA9)
F14
A_DDR3_A[0]
A_DDR3_A0
B_DDR3_A0
B13
A_DDR3_A[1]
A_DDR3_A1
B_DDR3_A1
E13
A_DDR3_A[2]
A_DDR3_A2
B_DDR3_A2
D13
A_DDR3_A[3]
A_DDR3_A3
B_DDR3_A3
C14
A_DDR3_A[4]
A_DDR3_A4
B_DDR3_A4
F13
A_DDR3_A[5]
A_DDR3_A5
B_DDR3_A5
C13
A_DDR3_A[6]
A_DDR3_A6
B_DDR3_A6
B10
A_DDR3_A[7]
A_DDR3_A7
B_DDR3_A7
A12
A_DDR3_A[8]
A_DDR3_A8
B_DDR3_A8
C10
A_DDR3_A[9]
A_DDR3_A9
B_DDR3_A9
A14
A_DDR3_A[10]
A_DDR3_A10
B_DDR3_A10
B12
A_DDR3_A[11]
A_DDR3_A11
B_DDR3_A11
F15
A_DDR3_A[12]
A_DDR3_A12
B_DDR3_A12
C11
A_DDR3_A[13]
A_DDR3_A13
B_DDR3_A13
C12
A_DDR3_A[14]
A_DDR3_A14
B_DDR3_A14
D17
A_DDR3_A[15]
A_DDR3_A15
B_DDR3_A15
E14
A_DDR3_BA[0]
A_DDR3_BA0
B_DDR3_BA0
B14
A_DDR3_BA[1]
A_DDR3_BA1
B_DDR3_BA1
E15
A_DDR3_BA[2]
A_DDR3_BA2
B_DDR3_BA2
E17
A_DDR3_RASZ
A_DDR3_RASZ
B_DDR3_RASZ
C17
A_DDR3_CASZ
A_DDR3_CASZ
B_DDR3_CASZ
C16
A_DDR3_WEZ
A_DDR3_WEZ
B_DDR3_WEZ
F17
A_DDR3_ODT
A_DDR3_ODT
B_DDR3_ODT
C15
A_DDR3_CKE
A_DDR3_CKE
B_DDR3_CKE
B11
A_DDR3_RESET
A_DDR3_RESETB
B_DDR3_RESETB
B16
A_DDR3_MCLK
A_DDR3_MCLK
B_DDR3_MCLK
A16
A_DDR3_MCLKZ
A_DDR3_MCLKZ
B_DDR3_MCLKZ
C9
A_DDR3_CSB1
A_DDR3_CSB1
B_DDR3_CSB1
A9
A_DDR3_CSB2
A_DDR3_CSB2
B_DDR3_CSB2
A_DDR3_DQ[0-15]
D23
A_DDR3_DQ[0]
A_DDR3_DQ0
B_DDR3_DQ0
A_DDR3_DQ[1]
A19
A_DDR3_DQ1
B_DDR3_DQ1
A_DDR3_DQ[2]
E22
A_DDR3_DQ2
B_DDR3_DQ2
B18
A_DDR3_DQ[3]
A_DDR3_DQ3
B_DDR3_DQ3
A_DDR3_DQ[4]
C23
A_DDR3_DQ4
B_DDR3_DQ4
A_DDR3_DQ[5]
C18
A_DDR3_DQ5
B_DDR3_DQ5
B22
A_DDR3_DQ[6]
A_DDR3_DQ6
B_DDR3_DQ6
A_DDR3_DQ[7]
A18
A_DDR3_DQ7
B_DDR3_DQ7
A_DDR3_DQ[8]
E19
A_DDR3_DQ8
B_DDR3_DQ8
A_DDR3_DQ[9]
B21
A_DDR3_DQ9
B_DDR3_DQ9
A_DDR3_DQ[10]
F18
A_DDR3_DQ10
B_DDR3_DQ10
A_DDR3_DQ[11]
C22
A_DDR3_DQ11
B_DDR3_DQ11
A_DDR3_DQ[12]
D20
A_DDR3_DQ12
B_DDR3_DQ12
A_DDR3_DQ[13]
F22
A_DDR3_DQ13
B_DDR3_DQ13
A_DDR3_DQ[14]
E18
A_DDR3_DQ14
B_DDR3_DQ14
A_DDR3_DQ[15]
D22
A_DDR3_DQ15
B_DDR3_DQ15
B19
A_DDR3_DM0
A_DDR3_DM0
B_DDR3_DM0
E21
A_DDR3_DM1
A_DDR3_DM1
B_DDR3_DM1
A21
A_DDR3_DQS0
A_DDR3_DQS0
B_DDR3_DQS0
B20
A_DDR3_DQS0B
A_DDR3_DQS0B
B_DDR3_DQS0B
C20
A_DDR3_DQS1
A_DDR3_DQS1
B_DDR3_DQS1
C19
A_DDR3_DQS1B
A_DDR3_DQS1B
B_DDR3_DQS1B
A_DDR3_DQ[16-31]
A_DDR3_DQ[16]
B27
A_DDR3_DQ16
B_DDR3_DQ16
A_DDR3_DQ[17]
A24
A_DDR3_DQ17
B_DDR3_DQ17
C27
A_DDR3_DQ[18]
A_DDR3_DQ18
B_DDR3_DQ18
A_DDR3_DQ[19]
C24
A_DDR3_DQ19
B_DDR3_DQ19
A_DDR3_DQ[20]
A28
A_DDR3_DQ20
B_DDR3_DQ20
E24
A_DDR3_DQ[21]
A_DDR3_DQ21
B_DDR3_DQ21
A_DDR3_DQ[22]
B28
A_DDR3_DQ22
B_DDR3_DQ22
A_DDR3_DQ[23]
B23
A_DDR3_DQ23
B_DDR3_DQ23
D25
A_DDR3_DQ[24]
A_DDR3_DQ24
B_DDR3_DQ24
A_DDR3_DQ[25]
E27
A_DDR3_DQ25
B_DDR3_DQ25
A_DDR3_DQ[26]
C25
A_DDR3_DQ26
B_DDR3_DQ26
D28
A_DDR3_DQ[27]
A_DDR3_DQ27
B_DDR3_DQ27
A_DDR3_DQ[28]
E26
A_DDR3_DQ28
B_DDR3_DQ28
A_DDR3_DQ[29]
E28
A_DDR3_DQ29
B_DDR3_DQ29
A_DDR3_DQ[30]
E25
A_DDR3_DQ30
B_DDR3_DQ30
A_DDR3_DQ[31]
C28
A_DDR3_DQ31
B_DDR3_DQ31
B24
A_DDR3_DM2
A_DDR3_DM2
B_DDR3_DM2
B26
A_DDR3_DM3
A_DDR3_DM3
B_DDR3_DM3
B25
A_DDR3_DQS2
A_DDR3_DQS2
B_DDR3_DQS2
A25
A_DDR3_DQS2B
A_DDR3_DQS2B
B_DDR3_DQS2B
D26
A_DDR3_DQS3
A_DDR3_DQS3
B_DDR3_DQS3
C26
A_DDR3_DQS3B
A_DDR3_DQS3B
B_DDR3_DQS3B
* DDR_VTT
+1.5V_U_DDR
R13100
IC13100
10K 1%
TPS51200DRCR
[EP]
R13101
C13122
10K
1000pF
REFIN
VIN
1%
1
10
VLDOIN
PGOOD
2
9
DDR_VTT_URSA
C13123
VO
GND
3
8
22uF
10V
L13100
PGND
EN
4
7
CIS21J121
VOSNS
REFOUT
5
6
C13110
C13111
C13113
10uF
10uF
10uF
Close to REFOUT pin
DDR_VTT_URSA
DDR_VTT_URSA_0
L13102
BLM18PG121SN1D
C13181
C13179
C13189
C13151
C13105
1uF
0.1uF
0.1uF
0.1uF
0.1uF
25V
16V
16V
16V
16V
DDR_VTT_URSA
DDR_VTT_URSA_1
L13103
BLM18PG121SN1D
C13112
C13132
C13158
C13174
C13106
1uF
0.1uF
0.1uF
0.1uF
0.1uF
25V
16V
16V
16V
16V
Decap removed
+1.5V_U_DDR
Close to DDR Power pin
C13104
C13109
C13117
C13128
C13137
C13146
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
16V
16V
16V
16V
16V
16V
+1.5V_U_DDR
Close to DDR Power pin
C13102
C13107
C13115
C13126
C13135
C13144
0.1uF
0.1uF
1uF
0.1uF
0.1uF
0.1uF
16V
16V
25V
16V
16V
16V
+1.5V_U_DDR
Close to DDR Power pin
Decap removed
C13103
C13108
C13116
0.1uF
0.1uF
0.1uF
16V
16V
16V
+1.5V_U_DDR
Close to DDR Power pin
Decap removed
C13195
0.1uF
16V
4th layer
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
DDR PHY VREF
B_DDR3_A[0-15]
H27
B_DDR3_A[0]
G31
B_DDR3_A[1]
+1.5V_U_DDR
+1.5V_U_DDR
U_MVREFCA_A0
U_MVREFCA_A1
G28
B_DDR3_A[2]
G29
B_DDR3_A[3]
H30
B_DDR3_A[4]
R13110
R13120
G27
B_DDR3_A[5]
1K
1K
1%
G30
B_DDR3_A[6]
1%
D31
B_DDR3_A[7]
F32
B_DDR3_A[8]
R13111
C13202
C13210
R13121
C13222
D30
B_DDR3_A[9]
1K
0.1uF
1000pF
1K
0.1uF
H32
B_DDR3_A[10]
1%
1%
F31
B_DDR3_A[11]
J27
B_DDR3_A[12]
E30
B_DDR3_A[13]
F30
B_DDR3_A[14]
L29
B_DDR3_A[15]
H28
B_DDR3_BA[0]
H31
B_DDR3_BA[1]
J28
B_DDR3_BA[2]
L28
B_DDR3_RASZ
L30
B_DDR3_CASZ
K30
B_DDR3_WEZ
L27
B_DDR3_ODT
J30
B_DDR3_CKE
E31
B_DDR3_RESET
K31
B_DDR3_MCLK
+1.5V_U_DDR
K32
+1.5V_U_DDR
B_DDR3_MCLKZ
U_MVREFCA_B0
C30
U_MVREFCA_B1
B_DDR3_CSB1
C32
B_DDR3_CSB2
B_DDR3_DQ[0-15]
R13108
U29
R13118
B_DDR3_DQ[0]
1K
1K
1%
N32
B_DDR3_DQ[1]
1%
T28
B_DDR3_DQ[2]
M31
B_DDR3_DQ[3]
R13109
C13201
C13209
U30
B_DDR3_DQ[4]
R13119
C13221
1K
0.1uF
1000pF
1K
0.1uF
M30
B_DDR3_DQ[5]
1%
1%
T31
B_DDR3_DQ[6]
M32
B_DDR3_DQ[7]
N28
B_DDR3_DQ[8]
R31
B_DDR3_DQ[9]
M27
B_DDR3_DQ[10]
T30
B_DDR3_DQ[11]
P29
B_DDR3_DQ[12]
T27
B_DDR3_DQ[13]
M28
B_DDR3_DQ[14]
T29
B_DDR3_DQ[15]
N31
B_DDR3_DM0
R28
B_DDR3_DM1
R32
B_DDR3_DQS0
P31
B_DDR3_DQS0B
P30
B_DDR3_DQS1
N30
B_DDR3_DQS1B
B_DDR3_DQ[16-31]
AA31
B_DDR3_DQ[16]
V32
B_DDR3_DQ[17]
AA30
B_DDR3_DQ[18]
V30
B_DDR3_DQ[19]
AB32
B_DDR3_DQ[20]
V28
B_DDR3_DQ[21]
+1.5V_U_DDR
A_DDR3_CKE
AB31
B_DDR3_DQ[22]
U31
B_DDR3_DQ[23]
R13102
R13112
W29
1K
1K
B_DDR3_DQ[24]
AA28
B_DDR3_DQ[25]
A_DDR3_RESET
W30
B_DDR3_DQ[26]
AB29
B_DDR3_DQ[27]
Y28
B_DDR3_DQ[28]
AB28
B_DDR3_DQ[29]
W28
B_DDR3_DQ[30]
AB30
B_DDR3_DQ[31]
+1.5V_U_DDR
B_DDR3_CKE
V31
B_DDR3_DM2
Y31
B_DDR3_DM3
R13113
R13103
1K
1K
W31
B_DDR3_DQS2
W32
B_DDR3_RESET
B_DDR3_DQS2B
Y29
B_DDR3_DQS3
Y30
B_DDR3_DQS3B
+3.3V_NORMAL
C13199
L13101
10uF
CIS21J121
10V
C13150
4700pF
C13147
0.1uF
C13156
C13164
C13172
C13178
C13186
C13194
C13198
C13206
C13214
C13218
C13226
0.1uF
0.1uF
1uF
0.1uF
0.1uF
10uF
0.1uF
0.1uF
0.1uF
0.1uF
1uF
16V
16V
25V
16V
16V
10V
16V
16V
16V
16V
25V
C13154
C13162
C13170
C13176
C13184
C13192
C13196
C13204
C13212
C13216
C13224
0.1uF
10uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
1uF
0.1uF
0.1uF
16V
10V
16V
16V
16V
16V
16V
16V
25V
16V
16V
C13230
1000pF
A_DDR3_A[0]
A_DDR3_A[1]
A_DDR3_A[2]
A_DDR3_A[3]
A_DDR3_A[4]
A_DDR3_A[5]
A_DDR3_A[6]
A_DDR3_A[7]
A_DDR3_A[8]
A_DDR3_A[9]
A_DDR3_A[10]
A_DDR3_A[11]
A_DDR3_A[12]
A_DDR3_A[13]
A_DDR3_A[15]
A_DDR3_MCLK
C13233
0.01uF
A_DDR3_MCLKZ
C13229
1000pF
A_DDR3_DQ[0-15]
B_DDR3_MCLK
C13234
0.01uF
B_DDR3_MCLKZ
B_DDR3_DQ[0-15]
C13232
C13100
C13101
0.1uF
10uF
10uF
16V
10V
10V
4th layer
DDR_VTT_URSA_1
IC2600
H5TQ1G63EFR-RDC
U_MVREFCA_A0
N3
M8
A0
VREFCA
P7
A_DDR3_A[0]
A1
P3
A_DDR3_A[1]
A2
N2
H1
A_DDR3_A[2]
A3
VREFDQ
P8
A_DDR3_A[3]
A4
P2
A_DDR3_A[4]
A5
R8
L8
R13126
240
A_DDR3_A[5]
A6
ZQ
R2
1%
A_DDR3_A[6]
A7
+1.5V_U_DDR
T8
A_DDR3_A[7]
A8
R3
B2
A_DDR3_A[8]
A9
VDD_1
L7
D9
A_DDR3_A[9]
A10/AP
VDD_2
R7
G7
A_DDR3_A[10]
A11
VDD_3
N7
K2
A_DDR3_A[11]
A12/BC
VDD_4
T3
K8
A_DDR3_A[12]
NC_7
VDD_5
N1
A_DDR3_A[13]
VDD_6
M7
N9
A_DDR3_A[14]
NC_5
VDD_7
R1
A_DDR3_A[15]
VDD_8
M2
R9
A_DDR3_BA[0]
BA0
VDD_9
N8
A_DDR3_BA[0]
A_DDR3_BA[1]
BA1
+1.5V_U_DDR
M3
A_DDR3_BA[1]
A_DDR3_BA[2]
BA2
A1
A_DDR3_BA[2]
VDDQ_1
J7
A8
CK
VDDQ_2
K7
C1
A_DDR3_MCLK
CK
VDDQ_3
K9
C9
A_DDR3_MCLKZ
A_DDR3_CKE
CKE
VDDQ_4
D2
A_DDR3_CKE
VDDQ_5
L2
E9
CS
VDDQ_6
A_DDR3_CSB1
K1
F1
A_DDR3_CSB2
A_DDR3_ODT
ODT
VDDQ_7
J3
H2
A_DDR3_ODT
A_DDR3_RASZ
RAS
VDDQ_8
K3
H9
A_DDR3_RASZ
A_DDR3_CASZ
CAS
VDDQ_9
L3
A_DDR3_CASZ
A_DDR3_WEZ
WE
J1
A_DDR3_WEZ
NC_1
T2
J9
A_DDR3_RESET
RESET
NC_2
L1
A_DDR3_RESET
NC_3
L9
NC_4
F3
T7
A_DDR3_A[14]
A_DDR3_DQS0
DQSL
NC_6
G3
A_DDR3_DQS0B
DQSL
C7
A9
A_DDR3_DQS1
DQSU
VSS_1
B7
B3
A_DDR3_DQS1B
DQSU
VSS_2
E1
VSS_3
E7
G8
A_DDR3_DM0
DML
VSS_4
D3
J2
A_DDR3_DM1
DMU
VSS_5
J8
VSS_6
A_DDR3_DQ[0]
E3
M1
DQL0
VSS_7
A_DDR3_DQ[1]
F7
M9
DQL1
VSS_8
F2
P1
A_DDR3_DQ[2]
DQL2
VSS_9
A_DDR3_DQ[3]
F8
P9
DQL3
VSS_10
A_DDR3_DQ[4]
H3
T1
DQL4
VSS_11
H8
T9
A_DDR3_DQ[5]
DQL5
VSS_12
A_DDR3_DQ[6]
G2
DQL6
A_DDR3_DQ[7]
H7
DQL7
B1
VSSQ_1
A_DDR3_DQ[8]
D7
B9
DQU0
VSSQ_2
A_DDR3_DQ[9]
C3
D1
DQU1
VSSQ_3
A_DDR3_DQ[10]
C8
D8
DQU2
VSSQ_4
A_DDR3_DQ[11]
C2
E2
DQU3
VSSQ_5
A_DDR3_DQ[12]
A7
E8
DQU4
VSSQ_6
A_DDR3_DQ[13]
A2
F9
DQU5
VSSQ_7
A_DDR3_DQ[14]
B8
G1
DQU6
VSSQ_8
A_DDR3_DQ[15]
A3
G9
DQU7
VSSQ_9
DDR_VTT_URSA_0
IC2800
H5TQ1G63EFR-RDC
U_MVREFCA_B0
B_DDR3_A[0]
B_DDR3_A[1]
N3
M8
B_DDR3_A[0]
A0
VREFCA
B_DDR3_A[2]
P7
B_DDR3_A[1]
A1
B_DDR3_A[3]
P3
B_DDR3_A[2]
A2
B_DDR3_A[4]
N2
H1
B_DDR3_A[3]
A3
VREFDQ
B_DDR3_A[5]
P8
B_DDR3_A[4]
A4
B_DDR3_A[6]
P2
B_DDR3_A[5]
A5
B_DDR3_A[7]
R8
L8
R13127
240
B_DDR3_A[6]
A6
ZQ
B_DDR3_A[8]
R2
1%
B_DDR3_A[7]
A7
+1.5V_U_DDR
B_DDR3_A[9]
T8
B_DDR3_A[8]
A8
B_DDR3_A[10]
R3
B2
B_DDR3_A[9]
A9
VDD_1
B_DDR3_A[11]
L7
D9
B_DDR3_A[10]
A10/AP
VDD_2
B_DDR3_A[12]
R7
G7
B_DDR3_A[11]
A11
VDD_3
B_DDR3_A[13]
N7
K2
B_DDR3_A[12]
A12/BC
VDD_4
B_DDR3_A[14]
T3
K8
B_DDR3_A[13]
NC_7
VDD_5
B_DDR3_A[15]
N1
VDD_6
M7
N9
B_DDR3_A[15]
NC_5
VDD_7
B_DDR3_BA[0]
R1
VDD_8
B_DDR3_BA[1]
M2
R9
B_DDR3_BA[0]
BA0
VDD_9
B_DDR3_BA[2]
N8
B_DDR3_BA[1]
BA1
M3
+1.5V_U_DDR
B_DDR3_BA[2]
BA2
A1
B_DDR3_MCLK
VDDQ_1
B_DDR3_MCLKZ
J7
A8
CK
VDDQ_2
B_DDR3_CKE
K7
C1
CK
VDDQ_3
K9
C9
B_DDR3_CKE
CKE
VDDQ_4
B_DDR3_CSB2
D2
VDDQ_5
B_DDR3_ODT
L2
E9
B_DDR3_CSB1
CS
VDDQ_6
K1
F1
B_DDR3_RASZ
B_DDR3_ODT
ODT
VDDQ_7
B_DDR3_CASZ
J3
H2
B_DDR3_RASZ
RAS
VDDQ_8
B_DDR3_WEZ
K3
H9
B_DDR3_CASZ
CAS
VDDQ_9
L3
B_DDR3_WEZ
WE
B_DDR3_RESET
J1
NC_1
T2
J9
B_DDR3_RESET
RESET
NC_2
L1
NC_3
L9
NC_4
F3
T7
B_DDR3_DQS0
DQSL
NC_6
B_DDR3_A[14]
G3
B_DDR3_DQS0B
DQSL
C7
A9
B_DDR3_DQS1
DQSU
VSS_1
B7
B3
B_DDR3_DQS1B
DQSU
VSS_2
E1
VSS_3
E7
G8
B_DDR3_DM0
DML
VSS_4
D3
J2
DMU
B_DDR3_DM1
VSS_5
J8
VSS_6
B_DDR3_DQ[0]
E3
M1
DQL0
VSS_7
B_DDR3_DQ[1]
F7
M9
DQL1
VSS_8
B_DDR3_DQ[2]
F2
P1
DQL2
VSS_9
B_DDR3_DQ[3]
F8
P9
DQL3
VSS_10
B_DDR3_DQ[4]
H3
T1
DQL4
VSS_11
B_DDR3_DQ[5]
H8
T9
DQL5
VSS_12
G2
B_DDR3_DQ[6]
DQL6
B_DDR3_DQ[7]
H7
DQL7
B1
VSSQ_1
D7
B9
B_DDR3_DQ[8]
DQU0
VSSQ_2
B_DDR3_DQ[9]
C3
D1
DQU1
VSSQ_3
B_DDR3_DQ[10]
C8
D8
DQU2
VSSQ_4
C2
E2
B_DDR3_DQ[11]
DQU3
VSSQ_5
B_DDR3_DQ[12]
A7
E8
DQU4
VSSQ_6
B_DDR3_DQ[13]
A2
F9
DQU5
VSSQ_7
B8
G1
B_DDR3_DQ[14]
DQU6
VSSQ_8
B_DDR3_DQ[15]
A3
G9
DQU7
VSSQ_9
IC2700
AR13100
AR13102
AR13104
AR13106
AR13108
AR13110
AR13112
H5TQ1G63EFR-RDC
100
100
100
100
100
100
100
U_MVREFCA_A1
N3
M8
A0
VREFCA
P7
A1
P3
A2
N2
H1
A3
VREFDQ
P8
A4
P2
A5
R8
L8
R13134
240
A6
ZQ
R2
1%
+1.5V_U_DDR
A7
T8
A8
R3
B2
A9
VDD_1
L7
D9
A10/AP
VDD_2
R7
G7
A11
VDD_3
N7
K2
A12/BC
VDD_4
T3
K8
NC_7
VDD_5
N1
VDD_6
M7
N9
NC_5
VDD_7
R1
VDD_8
M2
R9
BA0
VDD_9
N8
+1.5V_U_DDR
BA1
M3
BA2
A1
VDDQ_1
J7
A8
CK
VDDQ_2
K7
C1
CK
VDDQ_3
K9
C9
CKE
VDDQ_4
D2
VDDQ_5
L2
E9
CS
VDDQ_6
K1
F1
ODT
VDDQ_7
J3
H2
RAS
VDDQ_8
K3
H9
CAS
VDDQ_9
L3
WE
J1
NC_1
T2
J9
RESET
NC_2
L1
NC_3
L9
NC_4
F3
T7
A_DDR3_DQS2
DQSL
NC_6
A_DDR3_A[14]
G3
A_DDR3_DQS2B
DQSL
C7
A9
A_DDR3_DQS3
DQSU
VSS_1
B7
B3
A_DDR3_DQS3B
DQSU
VSS_2
E1
VSS_3
E7
G8
A_DDR3_DM2
DML
VSS_4
D3
J2
A_DDR3_DM3
DMU
VSS_5
J8
A_DDR3_DQ[16-31]
VSS_6
A_DDR3_DQ[16]
E3
M1
DQL0
VSS_7
F7
M9
A_DDR3_DQ[17]
DQL1
VSS_8
A_DDR3_DQ[18]
F2
P1
DQL2
VSS_9
A_DDR3_DQ[19]
F8
P9
DQL3
VSS_10
H3
T1
A_DDR3_DQ[20]
DQL4
VSS_11
A_DDR3_DQ[21]
H8
T9
DQL5
VSS_12
A_DDR3_DQ[22]
G2
DQL6
H7
A_DDR3_DQ[23]
DQL7
B1
VSSQ_1
A_DDR3_DQ[24]
D7
B9
DQU0
VSSQ_2
C3
D1
A_DDR3_DQ[25]
DQU1
VSSQ_3
A_DDR3_DQ[26]
C8
D8
DQU2
VSSQ_4
A_DDR3_DQ[27]
C2
E2
DQU3
VSSQ_5
A7
E8
A_DDR3_DQ[28]
DQU4
VSSQ_6
A_DDR3_DQ[29]
A2
F9
DQU5
VSSQ_7
A_DDR3_DQ[30]
B8
G1
DQU6
VSSQ_8
A_DDR3_DQ[31]
A3
G9
DQU7
VSSQ_9
IC2900
AR13101
AR13103
AR13105
AR13107
AR13109
AR13111
AR13113
100
100
100
100
100
100
100
H5TQ1G63EFR-RDC
U_MVREFCA_B1
N3
M8
A0
VREFCA
P7
A1
P3
A2
N2
H1
A3
VREFDQ
P8
A4
P2
A5
R8
L8
R13135
240
A6
ZQ
R2
1%
+1.5V_U_DDR
A7
T8
A8
R3
B2
A9
VDD_1
L7
D9
A10/AP
VDD_2
R7
G7
A11
VDD_3
N7
K2
A12/BC
VDD_4
T3
K8
NC_7
VDD_5
N1
VDD_6
M7
N9
NC_5
VDD_7
R1
VDD_8
M2
R9
BA0
VDD_9
N8
+1.5V_U_DDR
BA1
M3
BA2
A1
VDDQ_1
J7
A8
CK
VDDQ_2
K7
C1
CK
VDDQ_3
K9
C9
CKE
VDDQ_4
D2
VDDQ_5
L2
E9
CS
VDDQ_6
K1
F1
ODT
VDDQ_7
J3
H2
RAS
VDDQ_8
K3
H9
CAS
VDDQ_9
L3
WE
J1
NC_1
T2
J9
RESET
NC_2
L1
NC_3
L9
NC_4
F3
T7
B_DDR3_DQS2
DQSL
NC_6
B_DDR3_A[14]
G3
B_DDR3_DQS2B
DQSL
C7
A9
B_DDR3_DQS3
DQSU
VSS_1
B7
B3
B_DDR3_DQS3B
DQSU
VSS_2
E1
VSS_3
E7
G8
B_DDR3_DM2
DML
VSS_4
D3
J2
B_DDR3_DM3
DMU
VSS_5
J8
B_DDR3_DQ[16-31]
VSS_6
B_DDR3_DQ[16]
E3
M1
DQL0
VSS_7
F7
M9
B_DDR3_DQ[17]
DQL1
VSS_8
B_DDR3_DQ[18]
F2
P1
DQL2
VSS_9
B_DDR3_DQ[19]
F8
P9
DQL3
VSS_10
B_DDR3_DQ[20]
H3
T1
DQL4
VSS_11
B_DDR3_DQ[21]
H8
T9
DQL5
VSS_12
B_DDR3_DQ[22]
G2
DQL6
B_DDR3_DQ[23]
H7
DQL7
B1
VSSQ_1
B_DDR3_DQ[24]
D7
B9
DQU0
VSSQ_2
B_DDR3_DQ[25]
C3
D1
DQU1
VSSQ_3
B_DDR3_DQ[26]
C8
D8
DQU2
VSSQ_4
B_DDR3_DQ[27]
C2
E2
DQU3
VSSQ_5
B_DDR3_DQ[28]
A7
E8
DQU4
VSSQ_6
B_DDR3_DQ[29]
A2
F9
DQU5
VSSQ_7
B_DDR3_DQ[30]
B8
G1
DQU6
VSSQ_8
B_DDR3_DQ[31]
A3
G9
DQU7
VSSQ_9
BSD-14Y-UD-131-HD
THE
SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE
SYMBOL MARK OF THE SCHEMETIC.
2013.12.17
URSA7_DDR
LGE Internal Use Only
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