LG 77EG9700 Service Manual page 26

IC100
LG1154D_H13D
F15
M0_DDR_A[0] M0_DDR_A0
F13
M0_DDR_A[1] M0_DDR_A1
F17
M0_DDR_A2
M0_DDR_A[2]
F19
M0_DDR_A3
M0_DDR_A[3]
E10 M0_DDR_A0
M0_DDR_A[4] M0_DDR_A4
E18 M0_DDR_A1
M0_DDR_A[5] M0_DDR_A5
E11 M0_DDR_A2
M0_DDR_A[6] M0_DDR_A6
F18 M0_DDR_A3
M0_DDR_A[7] M0_DDR_A7
F11 M0_DDR_A4
M0_DDR_A[8] M0_DDR_A8
F16 M0_DDR_A5
M0_DDR_A9
M0_DDR_A[9]
E9 M0_DDR_A6
M0_DDR_A[10] M0_DDR_A10
E12 M0_DDR_A7
M0_DDR_A[11] M0_DDR_A11
E13 M0_DDR_A8
M0_DDR_A[12] M0_DDR_A12
E16 M0_DDR_A9
M0_DDR_A[13] M0_DDR_A13
F12 M0_DDR_A10
M0_DDR_A[14] M0_DDR_A14
F14 M0_DDR_A11
M0_DDR_A15
M0_DDR_A[15]
M0_DDR_A12
E19 M0_DDR_A13
M0_DDR_BA[0] M0_DDR_BA0
F10 M0_DDR_A14
M0_DDR_BA[1] M0_DDR_BA1
E15 M0_DDR_A15
M0_DDR_BA[2] M0_DDR_BA2
B10 M0_DDR_BA0
M0_DDR_U_CLK M0_U_CLK
A10 M0_DDR_BA1
M0_U_CLKN
M0_DDR_U_CLKN
A19 M0_DDR_BA2
M0_DDR_D_CLK M0_D_CLK
B19
M0_DDR_D_CLKN M0_D_CLKN
E14 M0_D_CLK
M0_DDR_CKE M0_DDR_CKE
M0_D_CLKN
F21 M0_DDR_CKE
M0_DDR_ODT M0_DDR_ODT
E21
M0_DDR_RASN
M0_DDR_RASN
E20
M0_DDR_CASN
M0_DDR_CASN
F20 M0_DDR_ODT
M0_DDR_WEN M0_DDR_WEN
M0_DDR_RASN
E17 M0_DDR_CASN
M0_DDR_RESET_N M0_DDR_RESET_N
M0_DDR_WEN
F9 240 R500
M0_DDR_ZQCAL
M0_DDR_RESET_N
1%
B20
M0_DDR_DQS[0] M0_DDR_DQS0
A20
M0_DDR_DQS_N[0] M0_DDR_DQS_N0
C19
M0_DDR_DQS[1] M0_DDR_DQS1
D19
M0_DDR_DQS_N[1] M0_DDR_DQS_N1
A11
M0_DDR_DQS[2] M0_DDR_DQS2
B11
M0_DDR_DQS_N2
M0_DDR_DQS_N[2]
C10
M0_DDR_DQS3
M0_DDR_DQS[3]
D10
M0_DDR_DQS_N[3] M0_DDR_DQS_N3
D18
M0_DDR_DM[0] M0_DDR_DM0
C20
M0_DDR_DM[1] M0_DDR_DM1
D9
M0_DDR_DM[2] M0_DDR_DM2
C11
M0_DDR_DM3
M0_DDR_DM[3]
D22
M0_DDR_DQ0
M0_DDR_DQ[0]
C15
M0_DDR_DQ[1] M0_DDR_DQ1
C23
M0_DDR_DQ[2] M0_DDR_DQ2
D16
M0_DDR_DQ[3] M0_DDR_DQ3
B24
M0_DDR_DQ4
M0_DDR_DQ[4]
B15
M0_DDR_DQ5
M0_DDR_DQ[5]
D23
M0_DDR_DQ6
M0_DDR_DQ[6]
A15
M0_DDR_DQ[7] M0_DDR_DQ7
C16
M0_DDR_DQ[8] M0_DDR_DQ8
D21
M0_DDR_DQ[9] M0_DDR_DQ9
D17
M0_DDR_DQ[10] M0_DDR_DQ10
C22
M0_DDR_DQ11
M0_DDR_DQ[11]
C18
M0_DDR_DQ12
M0_DDR_DQ[12]
C21
M0_DDR_DQ13
M0_DDR_DQ[13]
C17
M0_DDR_DQ[14] M0_DDR_DQ14
D20
M0_DDR_DQ[15] M0_DDR_DQ15
C13
M0_DDR_DQ[16] M0_DDR_DQ16
D7
M0_DDR_DQ17
M0_DDR_DQ[17]
D13
M0_DDR_DQ18
M0_DDR_DQ[18]
C6
M0_DDR_DQ19
M0_DDR_DQ[19]
D14
M0_DDR_DQ[20] M0_DDR_DQ20
D6
M0_DDR_DQ[21] M0_DDR_DQ21
C14
M0_DDR_DQ[22] M0_DDR_DQ22
A5
M0_DDR_DQ[23] M0_DDR_DQ23
C7
M0_DDR_DQ24
M0_DDR_DQ[24]
D12
M0_DDR_DQ25
M0_DDR_DQ[25]
D8
M0_DDR_DQ26
M0_DDR_DQ[26]
B13
M0_DDR_DQ[27] M0_DDR_DQ27
C9
M0_DDR_DQ[28] M0_DDR_DQ28
C12
M0_DDR_DQ[29] M0_DDR_DQ29
C8
M0_DDR_DQ30
M0_DDR_DQ[30]
D11
M0_DDR_DQ31
M0_DDR_DQ[31]
IC100
LG1154D_H13D
N6
M1_DDR_A0
M1_DDR_A[0]
R6
M1_DDR_A[1] M1_DDR_A1
L6
M1_DDR_A[2] M1_DDR_A2
J6
M1_DDR_A[3] M1_DDR_A3
U5
M1_DDR_A[4] M1_DDR_A4
J5
M1_DDR_A[5] M1_DDR_A5
T5
M1_DDR_A6
M1_DDR_A[6]
K6
M1_DDR_A7
M1_DDR_A[7]
U6
M1_DDR_A[8] M1_DDR_A8
M6
M1_DDR_A[9] M1_DDR_A9
V5
M1_DDR_A[10] M1_DDR_A10
R5
M1_DDR_A[11] M1_DDR_A11
P5
M1_DDR_A[12] M1_DDR_A12
L5
M1_DDR_A13
M1_DDR_A[13]
T6
M1_DDR_A[14] M1_DDR_A14
P6
M1_DDR_A[15] M1_DDR_A15
H5
M1_DDR_BA[0] M1_DDR_BA0
V6
M1_DDR_BA[1] M1_DDR_BA1
M5
M1_DDR_BA2
M1_DDR_BA[2]
R2
M1_DDR_U_CLK M1_U_CLK
R1
M1_DDR_U_CLKN M1_U_CLKN
F1
M1_DDR_D_CLK M1_D_CLK
F2
M1_DDR_D_CLKN M1_D_CLKN
N5
M1_DDR_CKE M1_DDR_CKE
G6
M1_DDR_ODT M1_DDR_ODT
F5
M1_DDR_RASN M1_DDR_RASN
G5
M1_DDR_CASN M1_DDR_CASN
H6
M1_DDR_WEN M1_DDR_WEN
K5
M1_DDR_RESET_N
M1_DDR_RESET_N
F6 240 R501
M1_DDR_ZQCAL
1%
E2
M1_DDR_DQS[0] M1_DDR_DQS0
E1
M1_DDR_DQS_N[0] M1_DDR_DQS_N0
F3
M1_DDR_DQS[1] M1_DDR_DQS1
F4
M1_DDR_DQS_N1
M1_DDR_DQS_N[1]
P1
M1_DDR_DQS[2] M1_DDR_DQS2
P2
M1_DDR_DQS_N[2] M1_DDR_DQS_N2
R3
M1_DDR_DQS[3] M1_DDR_DQS3
R4
M1_DDR_DQS_N[3] M1_DDR_DQS_N3
G4
M1_DDR_DM0
M1_DDR_DM[0]
E3
M1_DDR_DM1
M1_DDR_DM[1]
T4
M1_DDR_DM[2] M1_DDR_DM2
P3
M1_DDR_DM[3] M1_DDR_DM3
C4
M1_DDR_DQ[0] M1_DDR_DQ0
K3
M1_DDR_DQ[1] M1_DDR_DQ1
B3
M1_DDR_DQ2
M1_DDR_DQ[2]
J4
M1_DDR_DQ3
M1_DDR_DQ[3]
A3
M1_DDR_DQ4
M1_DDR_DQ[4]
K2
M1_DDR_DQ[5] M1_DDR_DQ5
B4
M1_DDR_DQ[6] M1_DDR_DQ6
K1
M1_DDR_DQ[7] M1_DDR_DQ7
J3
M1_DDR_DQ8
M1_DDR_DQ[8]
D4
M1_DDR_DQ9
M1_DDR_DQ[9]
H4
M1_DDR_DQ10
M1_DDR_DQ[10]
C3
M1_DDR_DQ[11] M1_DDR_DQ11
G3
M1_DDR_DQ[12] M1_DDR_DQ12
D3
M1_DDR_DQ[13] M1_DDR_DQ13
H3
M1_DDR_DQ[14] M1_DDR_DQ14
E4
M1_DDR_DQ15
M1_DDR_DQ[15]
M3
M1_DDR_DQ16
M1_DDR_DQ[16]
V4
M1_DDR_DQ[17] M1_DDR_DQ17
M4
M1_DDR_DQ[18] M1_DDR_DQ18
W3
M1_DDR_DQ[19] M1_DDR_DQ19
L4
M1_DDR_DQ[20] M1_DDR_DQ20
W4
M1_DDR_DQ21
M1_DDR_DQ[21]
L3
M1_DDR_DQ22
M1_DDR_DQ[22]
Y2
M1_DDR_DQ23
M1_DDR_DQ[23]
V3
M1_DDR_DQ[24] M1_DDR_DQ24
N4
M1_DDR_DQ[25] M1_DDR_DQ25
U4
M1_DDR_DQ[26] M1_DDR_DQ26
M2
M1_DDR_DQ[27] M1_DDR_DQ27
T3
M1_DDR_DQ28
M1_DDR_DQ[28]
N3
M1_DDR_DQ29
M1_DDR_DQ[29]
U3
M1_DDR_DQ30
M1_DDR_DQ[30]
P4
M1_DDR_DQ[31] M1_DDR_DQ31
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
Copyright ⓒ 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
IC500
M0_DDR_VREFCA
H5TQ4G83AFR-PBC
M0_DDR_VREFDQ
DDR3
K3 J8
M0_DDR_A0
A0 4Gbit VREFCA
L7 M0_DDR_A1
A1
L3
M0_DDR_A2
A2
K2 E1
M0_DDR_A3
A3 VREFDQ
L8
M0_DDR_A4
A4
L2
M0_DDR_A5
A5 R558 VDDC15_M0
M8 H8
M0_DDR_A6
A6 ZQ
M2 240 M0_DDR_A7
A7
1%
N8 M0_DDR_A8
A8
M3 A2
M0_DDR_A9
A9 VDD_1
H7 A9
M0_DDR_A10
A10/AP VDD_2
M7 D7
M0_DDR_A11
A11 VDD_3
K7 G2
M0_DDR_A12
A12/BC VDD_4
N3 G8
M0_DDR_A13
A13 VDD_5
N7 K1 M0_DDR_A14
A14 VDD_6
J7 K9
M0_DDR_A15
A15 VDD_7
M1
VDD_8
J2 M9
M0_DDR_BA0
BA0 VDD_9
K8
M0_DDR_BA1
BA1
J3
M0_DDR_BA2
BA2
B9
VDDQ_1
F7 C1 M0_D_CLK
CK VDDQ_2
G7 E2 C559 0.1uF
M0_D_CLKN
CK VDDQ_3
G9 E9 C560 0.1uF
M0_DDR_CKE
CKE VDDQ_4
H2
CS
G1
M0_DDR_ODT
ODT
F3 M0_DDR_RASN
RAS
G3
M0_DDR_CASN
CAS
H3
M0_DDR_WEN
WE
N2
M0_DDR_RESET_N
RESET
C3 M0_DDR_DQS1
M0_DDR_DQS0 DQS
D3
M0_DDR_DQS_N0 M0_DDR_DQS_N1
DQS
B7 A1
M0_DDR_DM1
M0_DDR_DM0 DM/TDQS VSS_1
A7 A8
NF/TDQS VSS_2
B1
VSS_3
D8
VSS_4
F2
VSS_5
F8
VSS_6
B3 J1
M0_DDR_DQ8
M0_DDR_DQ0 DQ0 VSS_7
C7 J9
M0_DDR_DQ9
M0_DDR_DQ1 DQ1 VSS_8
C2 L1
M0_DDR_DQ10
M0_DDR_DQ2 DQ2 VSS_9
C8
L9 M0_DDR_DQ11
M0_DDR_DQ3 DQ3 VSS_10
E3 N1 M0_DDR_DQ12
M0_DDR_DQ4 DQ4 VSS_11
E8 N9
M0_DDR_DQ5 M0_DDR_DQ13
DQ5 VSS_12
D2
M0_DDR_DQ14
M0_DDR_DQ6 DQ6
E7
M0_DDR_DQ15
M0_DDR_DQ7 DQ7
B2
VSSQ_1
A3 B8
NC_1 VSSQ_2
F1 C9
NC_2 VSSQ_3
F9 D1
NC_3 VSSQ_4
H1 D9
NC_4 VSSQ_5
H9
NC_5
VDDC15_M0
M0_DDR_CKE
R541
R520
10K
10K
M0_DDR_RESET_N
M0_U_CLK
M0_D_CLK
M0_D_CLKN M0_U_CLKN
M0_U_CLK
M0_D_CLK
M0_U_CLKN
M0_D_CLKN
VDDC15_M0
VDDC15_M0
VDDC15_M0
VDDC15_M0
M0_1_DDR_VREFCA
M0_DDR_VREFCA M0_1_DDR_VREFCA_T
M0_DDR_VREFCA_T
VDDC15_M0
VDDC15_M0
VDDC15_M0
VDDC15_M0
M0_1_DDR_VREFDQ
M0_1_DDR_VREFDQ_T
M0_DDR_VREFDQ M0_DDR_VREFDQ_T
IC502 IC504
M0_1_DDR_VREFCA
H5TQ4G83AFR-PBC H5TQ4G83AFR-PBC
M0_1_DDR_VREFDQ
DDR3
DDR3
K3 J8 K3 4Gbit
A0 VREFCA M0_DDR_A0 A0
4Gbit
L7 L7
M0_DDR_A1
A1 A1
L3 L3
A2 M0_DDR_A2 A2
K2 E1 K2
A3 VREFDQ M0_DDR_A3 A3
L8 L8
A4 M0_DDR_A4 A4
L2 L2
A5 R560 VDDC15_M0 M0_DDR_A5 A5
M8 H8 M8
A6 ZQ M0_DDR_A6 A6
M2 240 M2
M0_DDR_A7
A7 1% A7
N8 N8
M0_DDR_A8
A8 A8
M3 A2 M3
A9 VDD_1 M0_DDR_A9 A9
H7 A9 H7
A10/AP VDD_2 M0_DDR_A10 A10/AP
M7 D7 M7
A11 VDD_3 M0_DDR_A11 A11
K7 G2 K7
A12/BC VDD_4 M0_DDR_A12 A12/BC
N3 G8 N3
A13 VDD_5 M0_DDR_A13 A13
N7 K1 N7
M0_DDR_A14
A14 VDD_6 A14
J7 K9 J7
A15 VDD_7 M0_DDR_A15 A15
M1
VDD_8
J2 M9 J2
BA0 VDD_9 M0_DDR_BA0 BA0
K8 K8
BA1 M0_DDR_BA1 BA1
J3 J3
BA2 M0_DDR_BA2 BA2
B9
VDDQ_1
F7 C1 F7
M0_U_CLK
CK VDDQ_2 CK
G7 E2 C583 0.1uF G7
CK VDDQ_3 M0_U_CLKN CK
G9 E9 0.1uF G9
C574
CKE VDDQ_4 M0_DDR_CKE CKE
H2 H2
CS CS
G1 G1
ODT M0_DDR_ODT ODT
F3 F3
M0_DDR_RASN
RAS RAS
G3 G3
CAS M0_DDR_CASN CAS
H3 H3
WE M0_DDR_WEN WE
N2 N2
RESET M0_DDR_RESET_N RESET
C3 C3
M0_DDR_DQS2
DQS DQS
D3 D3
DQS M0_DDR_DQS_N2 DQS
B7 A1 B7
DM/TDQS VSS_1 M0_DDR_DM2 DM/TDQS
A7 A8 A7
NF/TDQS VSS_2 NF/TDQS
B1
VSS_3
D8
VSS_4
F2
VSS_5
F8
VSS_6
B3 J1 B3
DQ0 VSS_7 M0_DDR_DQ16 DQ0
C7 J9 C7
DQ1 VSS_8 M0_DDR_DQ17 DQ1
C2 L1 C2
DQ2 VSS_9 M0_DDR_DQ18 DQ2
C8 L9 C8
M0_DDR_DQ19
DQ3 VSS_10 DQ3
E3 N1 E3
M0_DDR_DQ20
DQ4 VSS_11 DQ4
E8 N9 E8
DQ5 VSS_12 M0_DDR_DQ21 DQ5
D2 D2
DQ6 M0_DDR_DQ22 DQ6
E7 E7
DQ7 M0_DDR_DQ23 DQ7
B2
VSSQ_1
A3 B8 A3
NC_1 VSSQ_2 NC_1
F1 C9 F1
NC_2 VSSQ_3 NC_2
F9 D1 F9
NC_3 VSSQ_4 NC_3
H1 D9 H1
NC_4 VSSQ_5 NC_4
H9 H9
NC_5 NC_5
DDR_SAMSUNG
K4B4G1646B-HCK0
N3
M1_DDR_A0 A0
P7
M1_DDR_A1
A1
P3
M1_DDR_A2
A2
N2
M1_DDR_A3 A3
P8
M1_DDR_A4 A4
P2
M1_DDR_A5 A5
R8
M1_DDR_A6 A6
R2
M1_DDR_A7 A7
T8
M1_DDR_A8
A8
R3
M1_DDR_A9 A9
L7
M1_DDR_A10 A10/AP
R7
M1_DDR_A11 A11
N7
M1_DDR_A12 A12/BC
T3
M1_DDR_A13 A13
T7
M1_DDR_A14
A14
M7
M1_DDR_A15
A15
M2
M1_DDR_BA0 BA0
N8
M1_DDR_BA1 BA1
M3
M1_DDR_BA2 BA2
VDDC15_M1 M1_DDR_CKE J7
M1_D_CLK
CK
K7
M1_D_CLKN CK
K9
R540 M1_DDR_CKE CKE
R521 10K
L2
10K CS
K1
M1_DDR_ODT ODT
J3
M1_DDR_RESET_N M1_DDR_RASN
RAS
K3
M1_DDR_CASN
CAS
L3
M1_DDR_WEN WE
M1_U_CLK
M1_D_CLK T2
M1_DDR_RESET_N RESET
F3
M1_DDR_DQS0
DQSL
G3
M1_D_CLKN M1_U_CLKN
M1_DDR_DQS_N0 DQSL
C7
M1_DDR_DQS1 DQSU
B7
M1_DDR_DQS_N1 DQSU
E7
M1_DDR_DM0
DML
D3
M1_DDR_DM1
DMU
E3
M1_DDR_DQ0 DQL0
F7
VDDC15_M1 VDDC15_M1 M1_DDR_DQ1 DQL1
F2
M1_DDR_DQ2 DQL2
M1_1_DDR_VREFCA F8
M1_DDR_DQ3 DQL3
M1_DDR_VREFCA
H3
M1_DDR_DQ4
DQL4
H8
M1_DDR_DQ5 DQL5
G2
M1_DDR_DQ6 DQL6
H7
M1_DDR_DQ7 DQL7
D7
M1_DDR_DQ8 DQU0
C3
M1_DDR_DQ9 DQU1
C8
M1_DDR_DQ10
DQU2
C2
M1_DDR_DQ11 DQU3
A7
M1_DDR_DQ12 DQU4
A2
M1_DDR_DQ13 DQU5
B8
M1_DDR_DQ14 DQU6
A3
M1_DDR_DQ15 DQU7
VDDC15_M1 VDDC15_M1 VDDC15_M1
M1_1_DDR_VREFDQ
M1_DDR_VREFDQ
Place at the bottom side
DDR_VTT
M0_DDR_VREFCA_T
AR8 AR9 AR11
AR7 AR10 AR12
56 56 56
56 56 56
M0_DDR_VREFDQ_T
J8
VREFCA
M0_DDR_A0
M0_DDR_A1
E1
VREFDQ M0_DDR_A2
M0_DDR_A3
R559 VDDC15_M0 M0_DDR_A4
H8
ZQ M0_DDR_A5
240
M0_DDR_A6
1%
M0_DDR_A7
A2
VDD_1 M0_DDR_A8
A9
VDD_2 M0_DDR_A9
D7
VDD_3 M0_DDR_A10
G2
VDD_4 M0_DDR_A11
G8
VDD_5 M0_DDR_A12
K1
M0_DDR_A13
VDD_6
K9
VDD_7 M0_DDR_A14
M1
VDD_8 M0_DDR_A15
M9
VDD_9
M0_DDR_BA0
M0_DDR_BA1
B9
M0_DDR_BA2
VDDQ_1
C1
VDDQ_2
E2 C568 0.1uF
VDDQ_3 M0_U_CLK
E9 0.1uF
C569
VDDQ_4 M0_U_CLKN
M0_DDR_CKE
M0_DDR_ODT
M0_DDR_RASN
M0_DDR_CASN
M0_DDR_WEN
M0_DDR_RESET_N
M0_DDR_DQS3
M0_DDR_DQS_N3
A1
VSS_1
A8
VSS_2 M0_DDR_DM3
B1
VSS_3
D8
VSS_4
F2
VSS_5
F8
VSS_6
J1
VSS_7
J9
VSS_8 M0_DDR_DQ24
L1
VSS_9 M0_DDR_DQ25
L9
M0_DDR_DQ26
VSS_10
N1
VSS_11 M0_DDR_DQ27
N9
VSS_12 M0_DDR_DQ28
M0_DDR_DQ29
M0_DDR_DQ30
B2
VSSQ_1 M0_DDR_DQ31
B8
VSSQ_2
C9
VSSQ_3
D1
VSSQ_4
D9
VSSQ_5
Real USE : 1Gbit
H5TQ1G63DFR-PBC(x16)
1Gbit : T7(NC_6)
IC501 4Gbit : T7(A14)
DDR_HYNIX
M1_DDR_VREFCA
IC501-*1
H5TQ4G63AFR-PBC
N3 M8
P7 A0 VREFCA
P3 A1
M1_DDR_VREFDQ N2 A3 A2 VREFDQ H1
P8 A4 N3
DDR3 M8 P2 A5 M1_DDR_A0
VREFCA R8 A6 ZQ L8
R2 A7 P7
4Gbit T8 A8
R3 A9 VDD_1 B2 M1_DDR_A1
L7 A10/AP VDD_2 D9 P3
R7 N7 A11 VDD_3 K2 G7
(x16) T3 A12/BC VDD_4 K8 M1_DDR_A2
T7 A13 VDD_5 N1 N2
H1 M7 A14 VDD_6 N9
A15 VDD_7 R1 M1_DDR_A3
VREFDQ M2 VDD_8 R9 P8
N8 BA0 VDD_9
M3 BA1 M1_DDR_A4
BA2 A1
J7 VDDQ_1 A8 P2
K7 CK CK VDDQ_3 VDDQ_2 C1 M1_DDR_A5
K9 CKE VDDQ_4 C9
L8 VDDQ_5 D2 R8
R543 240 L2 CS VDDQ_6 E9 M1_DDR_A6
ZQ K1 ODT VDDQ_7 F1
J3 RAS VDDQ_8 H2 R2
VDDC15_M1 K3 CAS VDDQ_9 H9
L3 WE J1 M1_DDR_A7
T2 NC_1 J9 T8
RESET NC_2 L1
NC_3 L9 M1_DDR_A8
F3 NC_4 R3
B2 G3 DQSL
DQSL M1_DDR_A9
VDD_1 C7 A9 L7
D9 B7 DQSU VSS_1 B3
DQSU VSS_2 E1 M1_DDR_A10
VDD_2 E7 DML VSS_4 VSS_3 G8
G7 D3 DMU VSS_5 J2 R7
VSS_6 J8 M1_DDR_A11
VDD_3 E3 DQL0 VSS_7 M1
K2 F7 DQL1 VSS_8 M9 N7
F2 DQL2 VSS_9 P1 M1_DDR_A12
VDD_4 F8 DQL3 VSS_10 P9
H3 DQL4 VSS_11 T1 T3
K8 G2 H8 DQL5 VSS_12 T9 M1_DDR_A13
VDD_5 H7 DQL6
DQL7 B1 T7
N1 D7 VSSQ_1 B9
C3 DQU0 VSSQ_2 D1 M1_DDR_A14
VDD_6 C8 DQU1 VSSQ_3 D8 M7
N9 C2 DQU2 VSSQ_4 E2
A7 DQU3 VSSQ_5 E8 M1_DDR_A15
VDD_7 A2 DQU4 VSSQ_6 F9
R1 B8 DQU5 VSSQ_7 G1
A3 DQU6 DQU7 VSSQ_8 VSSQ_9 G9
VDD_8 M2
R9
M1_DDR_BA0
VDD_9
N8
M1_DDR_BA1
M3
M1_DDR_BA2
A1
VDDQ_1
J7
A8
M1_U_CLK
VDDQ_2 K7
C1
M1_U_CLKN
VDDQ_3 K9
C9
M1_DDR_CKE
VDDQ_4
D2
VDDQ_5
E9 L2
VDDQ_6
K1
F1 M1_DDR_ODT
VDDQ_7
J3
H2 C529 0.1uF
M1_DDR_RASN
VDDQ_8 K3
H9 C530
0.1uF M1_DDR_CASN
VDDQ_9 L3
M1_DDR_WEN
J1
NC_1
J9 T2
M1_DDR_RESET_N
NC_2
L1
NC_3
L9
NC_4
F3
M1_DDR_DQS2
G3
M1_DDR_DQS_N2
A9 C7
M1_DDR_DQS3
VSS_1
B3 B7
M1_DDR_DQS_N3
VSS_2
E1
VSS_3
E7
G8
M1_DDR_DM2
VSS_4 D3
J2
M1_DDR_DM3
VSS_5
J8
VSS_6 E3
M1
M1_DDR_DQ16
VSS_7
M9 F7
M1_DDR_DQ17
VSS_8
P1 F2
M1_DDR_DQ18
VSS_9
F8
P9 M1_DDR_DQ19
VSS_10
H3
T1
M1_DDR_DQ20
VSS_11 H8
T9
M1_DDR_DQ21
VSS_12 G2
M1_DDR_DQ22
H7
M1_DDR_DQ23
B1
VSSQ_1
D7
B9 M1_DDR_DQ24
VSSQ_2
C3
D1
M1_DDR_DQ25
VSSQ_3 C8
D8
M1_DDR_DQ26
VSSQ_4 C2
E2
M1_DDR_DQ27
VSSQ_5 A7
E8
M1_DDR_DQ28
VSSQ_6
F9 A2
M1_DDR_DQ29
VSSQ_7
G1 B8
M1_DDR_DQ30
VSSQ_8
A3
G9 M1_DDR_DQ31
VSSQ_9
* DDR_VTT
VDDC15_M0
+3.3V_NORMAL
R546 IC506
10K 1% TPS51200DRCR [EP] L501
UBW2012-121F
R549 C510
10K 1000pF
REFIN VIN
1% 1 10
VLDOIN PGOOD C515
2 9
4700pF
DDR_VTT VO GND
C511
3 8
22uF
10V
PGND EN
L500
4 7
UBW2012-121F
VOSNS REFOUT
5 6
C503 C506 C507 C514
22uF 22uF 22uF 0.1uF
10V 10V 10V
Close to REFOUT pin
R3104 IC505
M0_1_DDR_VREFCA_T
56
H5TQ4G83AFR-PBC
M0_1_DDR_VREFDQ_T
DDR3
K3 J8
A0 4Gbit VREFCA
L7
A1
L3
A2
K2 E1
A3 VREFDQ
L8
A4
L2
A5 VDDC15_M0
R561
M8 H8
A6 ZQ
M2 240
A7 1%
N8
A8
M3 A2
A9 VDD_1
H7 A9
A10/AP VDD_2
M7 D7
A11 VDD_3
K7 G2
A12/BC VDD_4
N3 G8
A13 VDD_5
N7 K1
A14 VDD_6
J7 K9
A15 VDD_7
M1
VDD_8
J2 M9
BA0 VDD_9
K8
BA1
J3
BA2
B9
VDDQ_1
F7 C1
CK VDDQ_2
G7 E2 0.1uF
C572
CK VDDQ_3
G9 E9 0.1uF
C577
CKE VDDQ_4
H2
CS
G1
ODT
F3
RAS
G3
CAS
H3
WE
N2
RESET
C3
DQS
D3
DQS
B7 A1
DM/TDQS VSS_1
A7 A8
NF/TDQS VSS_2
B1
VSS_3
D8
VSS_4
F2
VSS_5
F8
VSS_6
B3 J1
DQ0 VSS_7
C7 J9
DQ1 VSS_8
C2 L1
DQ2 VSS_9
C8 L9
DQ3 VSS_10
E3 N1
DQ4 VSS_11
E8 N9
DQ5 VSS_12
D2
DQ6
E7
DQ7
B2
VSSQ_1
A3 B8
NC_1 VSSQ_2
F1 C9
NC_2 VSSQ_3
F9 D1
NC_3 VSSQ_4
H1 D9
NC_4 VSSQ_5
H9
NC_5
DDR_SAMSUNG
IC503
DDR_HYNIX
M1_1_DDR_VREFCA IC503-*1
K4B4G1646B-HCK0
H5TQ4G63AFR-PBC
N3 A0 VREFCA M8
P7 A1
P3 N2 A2 H1
P8 A3 VREFDQ
M1_1_DDR_VREFDQ P2 A4
DDR3 M8 R8 A5 L8
R2 A6 ZQ
A0 VREFCA T8 A7
4Gbit R3 A8 B2
L7 A9 VDD_1 D9
A1 R7 A10/AP VDD_2 G7
N7 A11 VDD_3 K2
(x16) T3 A13 A12/BC VDD_4 VDD_5 K8
A2 T7 A14 VDD_6 N1
H1 M7 A15 VDD_7 N9
VDD_8 R1
A3 VREFDQ M2 BA0 VDD_9 R9
N8 BA1
M3 BA2
A4 J7 VDDQ_1 A8 A1
K7 CK VDDQ_2 C1
K9 CK VDDQ_3 C9
A5 CKE VDDQ_4 D2
L2 VDDQ_5 E9
L8 R545 K1 CS VDDQ_6 F1
240 J3 ODT VDDQ_7 H2
A6 ZQ K3 RAS VDDQ_8 H9
L3 CAS VDDQ_9
WE J1
A7 VDDC15_M1 T2 RESET NC_1 NC_2 J9
NC_3 L1
NC_4 L9
A8 F3 DQSL
B2 G3 DQSL
A9 VDD_1 C7 DQSU VSS_1 A9
D9 B7 DQSU VSS_2 B3
E7 VSS_3 G8 E1
A10/AP VDD_2 D3 DML VSS_4 J2
DMU VSS_5 J8
G7 E3 VSS_6 M1
A11 VDD_3 F7 DQL0 VSS_7 M9
F2 DQL1 VSS_8 P1
K2 F8 DQL2 VSS_9 P9
H3 DQL3 VSS_10 T1
A12/BC VDD_4 H8 DQL4 VSS_11 T9
K8 G2 DQL5 VSS_12
H7 DQL7 DQL6
A13 VDD_5 VSSQ_1 B1
N1 D7 DQU0 VSSQ_2 B9
C3 DQU1 VSSQ_3 D1
A14 VDD_6 C8 DQU2 VSSQ_4 D8
N9 C2 DQU3 VSSQ_5 E2
A7 DQU4 VSSQ_6 E8
A15 VDD_7 A2 B8 DQU5 VSSQ_7 F9 G1
R1 A3 DQU6 VSSQ_8 G9
DQU7 VSSQ_9
VDD_8
R9
BA0 VDD_9
BA1
BA2
A1
VDDQ_1
A8
CK VDDQ_2
C1
CK VDDQ_3
C9
CKE VDDQ_4
D2
VDDQ_5
E9
CS
VDDQ_6
F1
ODT VDDQ_7
H2
C561 0.1uF
RAS VDDQ_8
H9
C562 0.1uF
CAS VDDQ_9
WE
J1
NC_1
J9
RESET NC_2
L1
NC_3
L9
NC_4
DQSL
DQSL
A9
DQSU VSS_1
B3
DQSU
VSS_2
E1
VSS_3
G8
DML VSS_4
J2
DMU VSS_5
J8
VSS_6
M1
DQL0 VSS_7
M9
DQL1 VSS_8
P1
DQL2 VSS_9
P9
DQL3 VSS_10
T1
DQL4 VSS_11
T9
DQL5 VSS_12
DQL6
DQL7
B1
VSSQ_1
B9
DQU0 VSSQ_2
D1
DQU1 VSSQ_3
D8
DQU2 VSSQ_4
E2
DQU3 VSSQ_5
E8
DQU4 VSSQ_6
F9
DQU5 VSSQ_7
G1
DQU6 VSSQ_8
G9
DQU7 VSSQ_9
DDR_VTT
C519 C520 C521 C522
0.47uF 0.47uF 0.47uF 0.47uF
6.3V 6.3V 6.3V 6.3V
BSD-14Y-UD-005-HD
2013-12-17
MAIN DDR
LGE Internal Use Only