LG 77EG9700 Service Manual page 81

D14 Block Diagram (Internal)
2.5V 3.3V
(AIP) (I/O)
LDO LDO
Serial/Parallel
TP Stream
DDR3PLL
XTAL
(24.75MHz)
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Only for training and service purposes
1.1V 1.5V
(Core) (DDR3)
LDO LDO
Boot
SPI I2C SRAM
ROM
VD0 VD1
HEVC1
ADO
HEVC2
TE PDEC
CortexM3
DCO
SSPLL DISPLL
Clock/Reset Gen
Serial Flash
ADO MCU0 MCU1 DMA
CPU Bus Interface (PL301)
VD2
H.264
Core1
H.264
H.264
Core2
(On2)
FHD
SDRAM
Memory Bus Interface (PL301)
Bus Architecture
lgm_top
DDR3 PHY (x32)
DDR3 PHY (x16)
x32
DDR3-1600
DDR3-1600
1Gbit
1Gbit
VD3
HDMI
VDO VCP
Link
lgm_top
x32
DDR3-1600
DDR3-1600
1Gbit
1Gbit
Analog IP
Added : D13 D14
Deleted : D13  D14
1920x2160@60p
HDMI
PHY
1920x2160@60p
HDMI
PHY
LGE Internal Use Only