Nera Inmarsat-c Service Manual page 29

1) Receiving part
Receiving circuit
The RF signal from the antenna unit is input to the receiving circuit by the diode switch,
CR20. FL13 of the receiving circuit is B.P.F of 1.5 GHz.
The BPSK modulating RF signal is changed to 1.2 kHz intermediate frequency at Hybrid
(U21) and DBM (U12 and U9) and then input to CPU (U14) as I and Q signals. The local
oscillator frequency input to DBM is 1.2 kHz lower than the receiving frequency.
The interference from MCA: Multi-Channel Access (1513 MHz to 1525 MHz) is reduced
by L.P.F consisted of inductor and capacitor (about 5 MHz) after changing the frequency at
U12/U9 (IF: 1.2 kHz).
At Hybrid, U21 and DBM, U12 and U9, the I signal and Q signal of 1.2 kHz IF signal are
taken from the BPSK modulated receiving RF signal to input to CPU, U14.
The Lissajous waveform is monitored by [J10]. AGC is controlled by the pin diodes, CR31
and CR32. The AGC signal is generated from the I signal and Q signal input to CPU. The
BPSK modulating signal is processed at U14 to send message to TERM CPU board.
The process of NCS/LES TDM channel signal processing at U14 (CPU) is as follows.
BPSK de-modulation (I signal and Q signal)
-- Detecting the unique word (Tuning the flame) -- De-permuting – De-Interleaving
-- Viterbi decoding -- De-scramble -- Taking the packet --
Sending to TERM CPU board
Fig.2.3.4 shows the block diagram of the RF CON/CPU receiving circuit.
Fig.2.3.4 Block diagram of RF CON/CPU receiving circuit
2-9
2.3 Terminal unit, IC-215