JVC MX-J570V Service Manual page 56

MX-J570V/MX-J680V
3.Pin function(1/2)
Pin No
13
178
190,174,156,153,147,141,138,
133,129,52,1
176
179
5,12,17,27,36,40,47,55,61,65,
69,75,81,87,91,95,101,107,113,
117,123,134,144,149,160,168,
175,181,193,197
7,14,19,29,38,42,49,57,63,67,
71,77,83,89,93,97,103,109,115,
119,125,136,146,151,162,170,
183,195,199
206
204-202
11-8,6,4-2
16
208
207
15
185
184
182
180
1-56
Name Symbol and I/O
System Services
RESET I
SYSCLK I
PIO[10:0] I/O
Power and Ground
A- VDD Analog
Power
A- VSS Analog Ground
VDD Power
VSS Ground
8-bit Host Interface
CS I
HADDR[2:0] I
HDAT[7:0] I/O
INT O,OD,PU
RD I
R/W I
WAIT O,OD,PU
CD interface
CD-C2PO I
CD-BCK I
CD-LRCK I
CD-DATA I
Description
Hardware reset. An external device asserts RESET (active LOW)
to execute a decoder hardware reset. To ensure proper initializat-
ion after power is stable, assert RESET for at least 20 s.
System clock. Decoder requires an external 27 MHz TTL oscillator.
Drive with the same 27-MHz as VCK.
Programmable I/O pins.
3.3-V analog supply voltage.
Analog ground for PLL.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
Host chip select. Host asserts CS to select the decoder for a read
or write operation. The falling edge of this signal triggers the read or
write operation.
Host address bus. 3-bit address bus selects one of eight host interf-
ace registers.
8-bit bi-directional host data bus. Host writes data to the decoder
Code FIFO via HDATA[7:0]. MSB of the 32-bit word is written
first. The host also reads and writes the decoder internal registers
and local SDRAM/ROM via HDAT[7:0].
Host interrupt. Open drain signal, must be pulled-up to 3.3 volts.
Driven high for 10 ns before tristate.
Read strobe in I mode. Must be held HIGH in M Mode.
Read/write strobe in M mode. Write strobe in I mode. Host asserts
R/W LOW to select write and LOW to select Read.
Active LOW to indicate host initiated transfer is not complete.
WAIT is asserted after the falling edge of CS and reasserted when
decoder is ready to complete transfer cycle. Open drain signal, mu-
st be pulled-up to 3.3 volts. Driven high for 10 ns before tristate.
Asserted HIGH indicates a corrupted byte. Decoder keeps the pre-
viouse valid picture on-screen until the next valid picture is decoded.
CD bit clock. Decoder accept multiple BCK rates.
Programmable polarity 16-bit word synchronization to the decoder
(right channel HIGH).
Serial CD data.