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MX-J570V/MX-J680V
LC72136N (IC2) : PLL frequency synthesizer
1. Pin layout
XT
1
FM/AM
2
CE
3
DI
4
CLOCK
5
DO
6
FM/ST/VCO
7
AM/FM
8
9
10
SDIN
11
2. Block diagram
1
22
16
15
3
4
C
B
2
I/F
5
6
Power
on
17
Reset
21
3. Pin function
Pin
Symbol
I/O
No.
X'tal oscillator connect (75kHz)
XT
I
1
LOW:FM mode
O
2
FM/AM
When data output/input for 4pin(input) and
CE
I
3
6pin(output): H
Input for receive the serial data from
DI
I
4
controller
Sync signal input use
CLOCK
I
5
Data output for Controller
DO
O
6
Output port
"Low": MW mode
O
7
FM/ST/VCO
Open state after the power on reset
AM/FM
O
8
Input/output port
I/O
9
LW
Input/output port
MW
I/O
10
Data input/output
SDIN
I/O
11
1-58
XT
22
GND
21
LPFOUT
20
LPFIN
19
PD
18
VCC
17
FMIN
16
AMIN
15
14
IFCONT
13
IFIN
12
Reference
Driver
Swallow Counter
Swallow Counter
1/2
1/16,1/17 4bit
1/16,1/17 4bit
12bit
Programmable
DriverS
Data Shift Register & Latch
11 13
7
8
2
Function
Phase
Detector
18
Charge Pump
19
20
Unlock
Detector
12
Universal
Counter
Pin
No.
Symbol
I/O
IF counter signal input
IFIN
I
12
IF signal output
IFCONT
O
13
Not use
14
-
AM Local OSC signal output
AMIN
I
15
FM Local OSC signal input
16
FMIN
I
Power suplly(VDD=4.5-5.5V)
17
VCC
-
When power ON:Reset circuit move
PLL charge pump output(H: Local OSC
PD
O
18
frequency Height than Reference frequency.
L: Low Agreement: Height impedance)
Input for active lowpassfilter of PLL
LPFIN
I
19
Output for active lowpassfilter of PLL
LPFOUT
O
20
Connected to GND
21
GND
-
X'tal oscillator(75KHz)
22
XT
I
Function
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