Denon ADV-700 Service Manual page 41

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3 7 63 1515 0
BA7625 (D/V : IC 302, 303)
BA7626 (D/V : IC 301)
Note 1: *mark means that feasible for either H or L.
Note 2: Each input terminal is porvided with sink chip clamp (BA7625).
Each input terminal takes 20kohm at the end (BA7626).
M66005FP (D/V : IC701)
TE
L 13942296513
D I G 1 1 1
2
D I G 1 0
D I G 0 9 3
D I G 0 8 4
D I G 0 7
5
DIGIT
D I G 0 6 6
OUTPUT
D I G 0 5
7
D I G 0 4
8
D I G 0 3
9
D I G 0 2
10
D I G 0 1
11
D I G 0 0
12
RESET IN
R E S E T 13
C S
CHIP SELECT IN 14
S C K 15
SHIFT CLOCK IN
S D A T A 16
SERIAL DATA IN
P I
17
OUTPUT PORT
P O 18
V c c 1
19
X O U T
20
CLOCK OUT
X I N
CLOCK IN 21
X s s
22
S E G 3 5 23
S E G 3 4 24
S E G 3 3
25
S E G 3 2 26
SEGMENT
S E G 3 1
27
OUTPUT
S E G 3 0
28
S E G 2 9 29
S E G 2 8
30
S E G 2 7
31
V p
32
TC74HCU04AF (D/V
1
1A
www
2
1Y
3
2A
4
2Y
.
5
3A
6
3Y
7
GND
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Monitor OUT
1
GND 2
IN5 3
OGIC
L
GND 4
IN4 5
CTL E 6
OGIC
IN3
7 L
CTL D
8
64 D I G 1 2
63
D I G 1 3
DIGIT
62 D I G 1 4
OUTPUT
D I G 1 5
61
V c c 2
60
S E G 0 0
59
S E G 0 1
58
S E G 0 2
57
S E G 0 3
56
S E G 0 4
55
S E G 0 5
54
S E G 0 6
53 Chip Select Input
52 S E G 0 7
Shift Clock Input
51 S E G 0 8
Serial Data Input
50 S E G 0 9
49 S E G 1 0
S E G 1 1
48
S E G 1 2
47
SEGMENT
S E G 1 3
46
OUTPUT
S E G 1 4
45
S E G 1 5
44
S E G 1 6
43
S E G 1 7
42
S E G 1 8
41 Reset Input
S E G 1 9
40
39 S E G 2 0
S E G 2 1
38
S E G 2 2
37
Clock Input
36 S E G 2 3
S E G 2 4
35
Clock Output
S E G 2 5
34
S E G 2 6
33
: IC304) SN74HC153NS (D/V: IC305)
1
Strobe 1G
14 Vcc
Select B 2
13 6A
3
1C
x ao 3
6Y
12
y
4
1C 2
Data
11
5A
Inputs
1C 5
1
i
10 5Y
1C 6
0
9 4A
7
Output 1Y
8 4Y 8
GND
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8
16
IN1
15 CTL A
6dB
14 VOUT1
13 Vcc
12
IN2
6dB
11 CTL B
10 VOUT2
CTL C
9
Q Q
3 6 7 1 3
Display Code Register
(8-bit x 16)
code
write
C S 1 4
Serial
Reception
SCK
1 5
Circuit
SDA TA 1 6
Code /
Command
Control Circ uit
Display Control
1 3
RESET
Register
Clock
XIN
2 1
Generatio n
Circuit
X OUT
2 0
BA4510F (DS: IC118, 119)
BA15218F (DS: IC115~117, 402, 601~603)
16
Vcc
NJM4558M (DVD: IC502)
15
2 2 G Strobe
1G
14 Select A
1C
3
u163
2G
1C
13
2 2C
3
2C
3
2C
2
1C 2C 12
1 2
Data
B B .
B Inputs
B
2C
1C 11 2C 1
1
0
A A
2C
1Y A 10 2C 0
A 0
2Y 9 2Y Output
2 9 9 4 2 8
NJU4053B V (D/V: IC308)
(Europe model only)
1
Y
1
Y1
2
Y
0 Y
0
3
Z
1 Z
1
4
Z
Z
5
Z
0 Z
0
6
Inhibit
Inhibit
V 7
EE
8
GND
BA7660FS (D/V
(Europe model only)
MUTE 1
2 6dB
INA
3
GND
INB 4 6dB
5
GND
6
N.C.
INC 7
6dB
8
GND
1 5 0 5 8 2 9 9 4
CGROM
(35-bit x 160 )
Segment
Output
Circuit
CGROM
(35-bit x 16)
RAM
write
Output P ort
(2-bit)
code selec t
Digit Output
Circuit
Display Cont r oller
(MA: IC503, 504, 606~609)
m
co
+
A OUTPUT
1 8
V
1
A INPUT 2 7 B OUTPUT
+
+
A INPUT
3 2 +
6 B INPUT
+
4 B INPUT
V 5
ADV-700
9 9
16
V
CC
15
Y
Y
14
X
X
13
X
X 1
1
12
X
X 0
0
11
A
A
10 B
C
B
9 C
: IC402, 403)
16
V
CC
75W
15
OUT A1
OUT A2
14
75W 13 OUTB1
12 OUTB2
11 N.C.
10 OUTC1
75W
9 OUTC2
2 8 9 9
SEG
5 9
00
SEG
3 3
Segment
26
Output
SEG
3 1
27
SEG
2 3
35
P0
1 8
Output P ort
P1
1 7
DIG
1 2
00
DIG
1
11
Digit Output
DIG
6 4
12
DIG
6 1
15
41