Denon adv-m71 Service Manual page 32

QQ
3 7 63 1515 0
74VHC573MTCX (DS: IC803,804)
1 20
OE
2 19
D0
3 18
D1
4 17
D2
16
D3 5
D4 6 15
D5 7 14
D6 8 13
D7 9 12
GND 10 11
SN74AHCT595PW (MA: IC306)
Q
1
B
Q
2
C
Q
3
D
Q
4
E
Q
5
F
Q
6
G
Q 7
H
GND 8
TE
L 13942296513
logic diagram (positive logic)
SRCLR
SRCLK
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Vcc
D0 D1 D2
Q0
2 3 4
Q1
Q2
D D
Q3
L
Q Q
Q4
L L
11
Q5
E
Q6
1
Q7
OE
19 18
LE
Q0 Q1
V SER SRCLK SRCLR
16
CC
Q X X
15
A
SER
14 X X
OE
13
X X
RCLK
12
L ↑
SRCLK
11
10 SRCLR
H
↑
9 Q
H'
X ↓
X X
X X
13
OE
12
RCLK
10
11
14
SER
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8
D3 D4 D5 D6
6 5 7 8
D D D D D
Q Q
Q Q Q
L L L L L
17 16 15 14 13
Q2 Q3 Q4 Q5 Q6
FUNCTION TABLE
INPUTS
RCLK OE
X X H Outputs Q A –Q H are disabled.
X X L Outputs Q A –Q H are enabled.
L X X Shift register is cleared.
First stage of the shift register goes low.
H X X
Other stages store the data of previous stage, respectively.
First stage of the shift register goes high.
H X X
Other stages store the data of previous stage, respectively.
H X X Shift-register state is not changed.
X ↑ X Shift-register data is stored in the storage register.
Q Q
3 6 7 1 3
X X Storage-register state is not changed.
↓
1D Q 3D
Q
C1 C3
R
2D Q 3D
Q
C2 C3
R
2D 3D
Q
Q
C2 C3
R
2D Q 3D
C2 C3 Q
R
2D Q 3D
C2 C3 Q
R
2D Q 3D
Q
C2 C3
R
2D Q 3D
C2 C3 Q
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R
.
2D Q 3D
Q
C2 C3
R
32
ADV-M71
2 9 9 4 2 8
PQ018EF01SZ (MA: IC706)
D7
9
D
FRONT
Q
VIEW
L
12
Q7
FUNCTION FUNCTION
1 5 0 5 8 2 9 9 4
15
Q A
1
Q B
2
Q C
3
Q D
4
Q E
5
Q F
m
6
Q G
co
7
Q H
9
Q H
32
9 9
2 8 9 9