Denon adv-m71 Service Manual page 15

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Pin No. Pin Name
97 XHPDIAGJ
92 XHDASPJ
102 XHIORDY
95, 96, 98 XHA[2:0]
106, 107, 108,
109, 111, 112,
113, 114, 116,
XHD[15.0]
117, 118, 119,
120, 121, 122,
123
143 XRSDCLK
147 XROEJ
142 XRWEJ
144 XRRASJ
145 XRCASJ
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L 13942296513
148, 149, 151,
152, 153, 155,
156, 157, 158, XRA[11:0]
159, 160, 161
124, 125, 126,
127, 128, 129,
131, 132, 134,
XRD[15:0]
135, 136, 137,
138, 139, 140,
141
4 AVDD5_DS
14 AVDD5_DA
26 AVDD5_AD
168 AVDD5_PL
7, 55, 58, 76,
115, 146,
VDD
150, 162
1 AVSS_DS
16 AVSS_DA
22 AVSS_AD
170 AVSS_PL
28, 42, 61,
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88, 110, 130,
GND
138, 154, 165
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Type
I/O This pin is used as the Passed Diagnostics signal, and may be an input or an open-drain output
This pin is used as the Drive Active/Slave Present signal, and is an input or an open-drain
I/O
output. This pin is used for Master/Slave drive communication and/or for driving an LED
1. I/O channel ready. This signal is driven low to extend host transfer cycles when the controller
is not ready to respond. This pin will be tri-stated when a read or write is not in progress.
I/O
2. MPEG error. This pin is used as the ERROR signal when MPEG interface mode is selected
Host address lines. The host address lines A[2:0] are used to access the various host control,
I
status, and data registers
1. Host data bus. This bus is used to transfer data and status between the host and the controller.
2. MPEG data bus 7-8. The HD[7:0] are used as the DATA [7:0] when MPEG interface mode is selected.
3. VCD I/F. Bit3-0 are used as VCD I/F signal when VCD function is enabled. The relationship of
bit3-0 and VCD I/F is as follow
I/O
O This signal is the clock output for SDRAM
This signal is used as the memory output enable for external DRAM buffers. After RSTJ is
O
asserted, this signal will be low
O This signal is asserted low when a buffer memory write operation is active
This signal is used as Row address output to external DRAM buffer. After RSTJ is asserted, this
O
signal will be high
This signal is used as column address output to external DRAM. After RSTJ is asserted, this
O
signal will be high
1. RAM address lines. These are bits11-0 for addressing the buffer memory.
2. Hardware setting. The bits6-0 are used as hardware setting for some functions.
RA[9] : FLASH size is 64K/128K
RA[8] : External CPU is 8032/H8
RA[7] : Microcontroller programmable I/O port 1 pin control
RA[6] : System test pin output
O
RA[5] : For testing purpose, don't need to set
RA[4] : IDE master/slave
RA[3] : For testing purpose, don't need to set
RA[2] : For testing purpose, don't need to set
RA[1-0] : MCU Mode selection
I/O These signals are the 8-bit parallel data lines to/from the buffer memory.
Analog Power +5V for Data Slicer part
Analog Power +5V for DAC part
Analog Power +5V for ADC part
Analog Power +5V for Data PLL part
Power +3.3V for digital core logic and pad
Analog Ground for Data Slicer part
Analog Ground for DAC part
Analog Ground for ADC part
Analog Ground for Data PLL part
Digital Ground core logic and pad.
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Description
HD0—CD-DATA
HD1—CD-LRCK
HD2—CD-BCK
HD3—CD-C2PO
1: FLASH size is 64K
0: FLASH size is 128K
1: 8032
0: H8
Q Q
1: By internal microcontroller 3 6 7 1 3 1 5
0: By registers to decide input/output
1: Normal operation
0: System test pin output
1: Slave
0: Master
11: Normal Mode (internal uP , internal address latch)
10: Outside uP Mode (ICE Mode)
01: Test mode for internal uP testing
00: Internal uP mode with external address latch
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