Denon adv-m71 Service Manual page 26

QQ
3 7 63 1515 0
T431616A-8S (ME: U5)
TE
L 13942296513
PIN DESCRIPTION
PIN
CLK
CS
CKE
A0 ~ A10/AP
BA
RAS
CAS
WE
L(U)DQM
DQ0 ~ DQ15
V /V
DD SS
www
V /V
DD Q SSQ
N.C/RFU
.
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V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
PIN NAME
Active on the positive going edge to sample all input.
System Clock
Disables or enables device operation by masking or enabling all input
Chip Select
except CLK,CKE and L(U)DQM
Clock Enable
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
x ao
y
No Connection/Reserved
i
for Future Use
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8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Q Q
3 6 7 1 3
DESCRIPTION
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column aaddresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
Selects bank to activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK
with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t after the clock and masks the output.
SHZ
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Powe and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
u163
This pin is recommended to be left No Connection on the device.
.
26
ADV-M71
2 9 9 4 2 8
50
V
SS
49
DQ15
48
DQ14
47
V
SSQ
46
DQ13
45
DQ12
44
V
DDQ
43
DQ11
42
DQ10
41
V
SSQ
40
DQ9
39
DQ8
38
V
DDQ
37
N . C / RFU
36
UDQM
35
CLK
34
CKE
33
N . C
32
A9
31
A8
30
A7
29
A6
28
A5
27
A4
26
V
SS
1 5 0 5 8 2 9 9 4
m
co
26
9 9
2 8 9 9