Aiwa xd-pg700 Service Manual page 58

IC DESCRIPTION -5/5 (NDV8601 -5/7)
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Pin No. Pin Name
157 AD[15]
158 AD[14]
159 VDD
160 SCLK
161 ACK
162 VSSIO
163 AD[13]
164 AD[12]
165 AD[11]
166 AD[10]
167 AD[9]
168 AD[8]
169 VDDIO
170 PWE[1]
171 VSS
172 AD[7]
173 AD[6]
174 AD[5]
TE
175 AD[4]
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176 AD[3]
177 VSSIO
178 AD[2]
179 AD[1]
180 AD[0]
181 VDDIO
182 PWE[0]
183 ALE
184 LA[0]
185 LA[1]
186 LA[2]
187 LA[3]
188 VSSIO
189 RD
190 LHLDA
191 LHLD
192 VDD
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193 PCS0
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I/O
B µP multiplexed address/data bus 15
B µP multiplexed address/data bus 14
P Core Power=1.8V
O External bus clock used for programmable host bus peripherals
B Programmable WAIT-/ACK-/RDY- control
P I/O Pad ground
B µP multiplexed address/data bus 13
B µP multiplexed address/data bus 12
B µP multiplexed address/data bus 11
B µP multiplexed address/data bus 10
B µP multiplexed address/data bus 9
B µP multiplexed address/data bus 8
P I/O Pad power=3.3V
Byte write enable for FLASH, Electrically Erasable Programmable Read-Only Memory (EEPROM),
B
static random access memory (SRAM) or peripherals
P Core and Ring Ground
B µP multiplexed address/data bus 7
B µP multiplexed address/data bus 6
B µP multiplexed address/data bus 5
B µP multiplexed address/data bus 4
B µP multiplexed address/data bus 3
P I/O Pad ground
B µP multiplexed address/data bus 2
B µP multiplexed address/data bus 1
B µP multiplexed address/data bus 0
P I/O Pad power=3.3V
Byte write enable for FLASH, Electrically Erasable Programmable Read-Only Memory (EEPROM),
B
static random access memory (SRAM) or peripherals
B ALE
B Latched Address 0
B Latched Address 1
B Latched Address 2
B Latched Address 3
P I/O Pad ground
B Read
O Bus Hold Acknowledge in slave mode
I Bus Hold Request from external master in slave mode
P Core Power=1.8V
Peripheral chip select 0, generally used for enabling the program store read-only memory (ROM)/
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FLASH
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Description
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