Aiwa xd-pg700 Service Manual page 55

IC DESCRIPTION -5/5 (NDV8601 -2/7)
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Pin No. Pin Name
42 DQM[2]
43 MD[16]
44 VDDIO
45 MD[17]
46 MD[18]
47 VSS
48 MD[19]
49 VSSIO
50 MD[20]
51 MD[21]
52 MD[22]
53 VDDIO
54 MD[23]
55 MD[24]
56 MD[25]
57 VSSIO
58 MD[26]
59 MD[27]
60 MD[28]
TE
61 MD[29]
L 13942296513
62 VDDIO
63 MD[30]
64 MD[31]
65 DQM[3]
66 CS1
67 VSSIO
68 SPDIF
69 VSS
70 AIN
71 AOUT3
72 AOUT2
73 AOUT1
74 AOUT0
75 VDDIO
76 PCMCLK
77 VDD
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78 ACLK
79 LRCLK
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80 SRST
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I/O
O SDRAM data byte enables 2
B SDRAM data bus 16
P I/O Pad power=3.3V
B SDRAM data bus 17
B SDRAM data bus 18
P Core and Ring Ground
B SDRAM data bus 19
P I/O Pad ground
B SDRAM data bus 20
B SDRAM data bus 21
B SDRAM data bus 22
P I/O Pad power=3.3V
B SDRAM data bus 23
B SDRAM data bus 24
B SDRAM data bus 25
P I/O Pad ground
B SDRAM data bus 26
B SDRAM data bus 27
B SDRAM data bus 28
B SDRAM data bus 29
P I/O Pad power=3.3V
B SDRAM data bus 30
B SDRAM data bus 31
O SDRAM data byte enables 3
O SDRAM extension bank chip select
P I/O Pad ground
O S/PDIF digital audio output
P Core and Ring Ground
I Digital audio input for digital micro; can be used as GPIO
Serial audio output data to audio DAC for Left and Right channels for down-mixed stereo; can be
O
used as GPIO
O Serial audio output data to audio DAC for Surround Left and Right channels; can be used as GPIO
O Serial audio output data to audio DAC for Center and LFE channels; can be used as GPIO
O Serial audio output data to audio DAC for Left and Right channels; can be used as GPIO
P I/O Pad power=3.3V
Audio DAC PCM sampling clock frequency, common clock for DACs and ADC; can be used as
O
GPIO
P Core Power=1.8V
O Audio interface serial data clock, common clock for DACs and analog-to-digital converter (ADC)
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O Left/Right Channel clock, common clock for DACs and ADC
i
O Active low RESET signal for peripheral reset Video Interface
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Description
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