Aiwa xd-pg700 Service Manual page 54

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IC DESCRIPTION -5/5 (NDV8601 -1/7)
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Pin No.
Pin Name
1
VDDIO
2
MD[10]
3
MD[11]
4
VDD
5
MD[12]
6
VSSIO
7
MD[13]
8
MD[14]
9
MD[15]
10
VDDIO
11
DQM[1]
12
MA[9]
13
MA[8]
14
VSSIO
15
MA[7]
16
MA[6]
17
VSS
18
MA[5]
19
VDDIO
TE
20
L 13942296513
MA[4]
21
MA[3]
22
MCLK
23
VSSIO
24
CKE
25
MA[2]
26
MA[1]
27
VDDIO
28
MA[0]
29
MA[10]
30
MA[11]
31
VSSIO
32
MA[12]
33
MA[13]
34
VDD
35
CS0
36
VDDIO
37
RAS
38
CAS
www
39
WE
40
VSSIO
.
41
DQM[0]
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I/O
P
I/O Pad power=3.3V
B
SDRAM data bus 10
B
SDRAM data bus 11
P
Core Power=1.8V
B
SDRAM data bus 12
P
I/O Pad ground
B
SDRAM data bus 13
B
SDRAM data bus 14
B
SDRAM data bus 15
P
I/O Pad power=3.3V
O
SDRAM data byte enables 1
O
SDRAM address bus 9
O
SDRAM address bus 8
P
I/O Pad ground
O
SDRAM address bus 7
O
SDRAM address bus 6
P
Core and Ring Ground
O
SDRAM address bus 5
P
I/O Pad power=3.3V
O
SDRAM address bus 4
O
SDRAM address bus 3
O
SDRAM clock
P
I/O Pad ground
O
SDRAM Clock Enable
O
SDRAM address bus 2
O
SDRAM address bus 1
P
I/O Pad power=3.3V
O
SDRAM address bus 0
O
SDRAM address bus 10
O
SDRAM address bus 11
P
I/O Pad ground
O
SDRAM address bus, reserved for pin compatibility with 64-Mb SDRAM
O
SDRAM address bus, reserved for pin compatibility with 64-Mb SDRAM
P
Core Power=1.8V
O
SDRAM primary bank chip select
P
I/O Pad power=3.3V
O
SDRAM
O
SDRAM
O
SDRAM
x
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y
P
I/O Pad ground
i
O
SDRAM data byte enables 0
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2 9
8
Description
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3
6 7
1 3
1 5
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2 8
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8
2 9
9 4
2 8
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9 9

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