Aiwa xd-pg700 Service Manual page 57

IC DESCRIPTION -5/5 (NDV8601 -4/7)
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Pin No. Pin Name
119 RSET
120 COMP
121 VSS
122 VIOCLK
123 VSYNC
124 HSYNC
125 VDDIO
126 VIO[7]
127 VIO[6]
128 VIO[5]
129 VIO[4]
130 VIO[3]
131 VIO[2]
132 VSSIO
133 VIO[1]
134 VIO[0]
135 VDD
136 AD[31]
TE
137 AD[30]
L 13942296513
138 AD[29]
139 AD[28]
140 VDDIO
141 AD[27]
142 AD[26]
143 AD[25]
144 AD[24]
145 PWE[3]
146 AD[23]
147 VSSIO
148 AD[22]
149 AD[21]
150 AD[20]
151 AD[19]
152 AD[18]
153 AD[17]
154 VDDIO
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155 AD[16]
156 PWE[2]
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I/O
O Current setting resistor of output DACs
O Compensation capacitor connection
P Core and Ring Ground
B VCLK input/output for Video I/O Port function
B Bi-directional VSYNC signal for devices that do not use EAV/SAV codes; can be used as GPIO
Bi-directional HSYNC signal for devices that do not use end active video/start active video (EAV/
B
SAV) codes; can be used as GPIO
P I/O Pad power=3.3V
B Bi-directional digital video port data bus; can be used as GPIO
P I/O Pad ground
B Bi-directional digital video port data bus; can be used as GPIO
P Core Power=1.8V
B µP multiplexed address/data bus 31
B µP multiplexed address/data bus 30
B µP multiplexed address/data bus 29
B µP multiplexed address/data bus 28
P I/O Pad power=3.3V
B µP multiplexed address/data bus 27
B µP multiplexed address/data bus 26
B µP multiplexed address/data bus 25
B µP multiplexed address/data bus 24
Byte write enable for FLASH, Electrically Erasable Programmable Read-Only Memory (EEPROM),
B
static random access memory (SRAM) or peripherals
B µP multiplexed address/data bus 23
P I/O Pad ground
B µP multiplexed address/data bus 22
B µP multiplexed address/data bus 21
B µP multiplexed address/data bus 20
B µP multiplexed address/data bus 19
B µP multiplexed address/data bus 18
B µP multiplexed address/data bus 17
P I/O Pad power=3.3V
B µP multiplexed address/data bus 16
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Byte write enable for FLASH, Electrically Erasable Programmable Read-Only Memory (EEPROM),
B
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static random access memory (SRAM) or peripherals
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Description
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