Atmel AT89C5132 Specification Sheet page 10

4.2 Internal Pin Structure
AT89C5132
10
Table 15. Detailed Internal Pin Structure
Watchdog Output
Latch Output
Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to the
Section "DC Characteristics", page 183.
2. When the Two Wire controller is enabled, P
pseudo open-drain structure.
3. In Port 2, P transistor is continuously driven when outputting a high level bit address (A15:8).
1
(1)
Circuit
VDD
VDD
P
VSS
VDD VDD VDD
2 osc
periods
P P P
1 2 3
N
VSS
VDD
P
N
VSS
VDD
P
N
VSS
D+
D-
Type
Input
Input/Output
Input/Output
Input/Output
Output
Input/Output
, P , and P transistors are disabled allowing
1 2 3
Pins
TST
RST
(2)
P1
(3)
P2
P3
P4
P53:0
P0
MCMD
MDAT
ISP
PSEN
ALE
SCLK
DCLK
DOUT
DSEL
MCLK
D+
D-
4173ES–USB–09/07