Sanyo PLC-XF47 Service Manual page 138

Electrical Adjustments
Pin No. Name Function Name Function Polarity I/O
146 WAIT
147 RESETM
148 ADTRG / PTH[5]
149 IOIS16 / PTG[7]
150 ASEMD0
151 PTG[5] / ASERKAK
152 PTG[4}
153 PCC0BVD2 / PTG[3] / AUDATA[3]
154 PCC0BVD1 / PTG[2] / AUDATA[2]
155 Vss
156 PCC0BCD2 / PTG[1] / AUDATA[1]
157 Vcc
158 PCC0BCD1 / PTG[0] / AUDATA[0]
159 VssQ
160 PTF[7] / PINT[15] / TRST
161 VccQ
162 PTF[6] / PINT[14] / TRST
163 PTF[5] / PINT[13] / TDI
164 PTF[4] / PINT[12] / TCK
165 PTF[3] / PINT[11]
166 PCCREG / PTF[2] / RESARVATION
167 PCCVS1 / PTF[1] / RESARVATION
168 PCCVS2 / PTF[0] / RESARVATION
169 MD0
170 Vcc_PLL1
171 CAP1
172 Vss_PLL1
173 Vss_PLL2
174 CAP2
175 Vcc_PLL2
176 PCC0WAIT / PTH[6] / AUDCK
177 Vss
178 Vcc
179 XTAL
180 EXTAL
181 LCD15 / PTM[3] / PINT[10]
182 LCD14 / PTM[2] / PINT[9]
183 LCD13 / PTM[1] / PINT[8]
184 LCD12 / PTM[0]
185 STATUS0 / PTJ[6]
186 STATUS1 / PTJ[7]
187 CL2
188 VssQ
189 CKIO
190 VccQ
191 TxD0 / SCPT[0]
192 SCK0 / SCPT[1]
193 TxD_SIO / SCPT[2]
194 SIOMCLK / SCPT[3]
195 TxD2 / SCPT[4]
196 SCK_SIO / SCPT[5]
197 SIOFSYNC / SCPT[6]
198 RxD0 / SCPT[0]
199 RxD_SIO / SCPT[2]
200 Vss
201 RxD2 / SCPT[4]
202 Vcc
203 SCPT[7] / CTS2 / IRQ5
204 LCD11 / PTC[7] / PINT[3]
205 LCD10 / PTC[6] / PINT[2]
206 LCD9 / PTC[5] / PINT[1]
207 VssQ
208 LCD8 / PTC[4] / PINT[0]
209 VccQ
210 LCD7 / PTD[3]
211 LCD6 / PTD[2]
212 LCD5 / PTC[3]
213 LCD4 / PTC[2]
214 LCD3 / PTC[1]
215 LCD2 / PTC[0]
216 LCD1 / PTD[1]
217 LCD0 / PTD[0]
218 DREQ0 / PTD[4]
219 LCK / UCLK PTD[6]
unused Hardware Wait
RESETM Manual Reset Demand
unused Analog Trigger / Input Port H
unused IOIS16(PCMCIA) / Input Port G
ASSEMD0[ICE] ASE Mode
ASEBRKAK [ICE] ASE Break Acknowlege
unused Input Port G
AUDATA[3] AUDATA[3]
AUDATA[2] AUDATA[2]
GND
AUDATA[1] AUDATA[1]
1.9V
AUDATA[1] AUDATA[0]
GND
TRST Test Reset
3.3V
TMS Test Mode Switch
TDI Test Data Input
TCK Test Clock
unused Input Port F / Port Interrupt / Resarvation
unused PCC REG / Input Port F / Resarvation
unused PCC VS1 / Input Port F / Resarvation
MOTHER_FPGA_NSTATUS Error Detect
MD0 Setting Clock Mode
1.9V Power PLL1
CAP1 PLL1 External Capacity Terminal
GND
GND
CAP2 PLL2 External Capacity Terminal
1.9V Power PLL1
AUDCK AUD Clock
GND
1.9V
unused Clock Oscilator
EXTAL External Clock / Crystal Oscilator [33.33333MHz]
MOTHER_FPGA_DONE AUD Clock / Configuration Process End Signal
SH_CHK_DPRAM PW_INT Clear Monitor (Input)
NIOS_FPGA_NSTATUS Error Detect
NIOS_FPGA_DONE Normary Ends Detect
READY_LED Ready LED Output
IC_RESET_CPU IC Power Conyrol
SH_FLASH_WP Flash Write Protect
GND
CKIO System Clock Input / Output
3.3V
SH_LB_UART Send Data (Network)
unused Serial Clock 0 / SCI IO Port
unused SIOF Send Data / SCI Output Port
unused SIOF Clock Input / SCI IO Port
SH_EX_UART Send Data ( External)
unused SIOFClock / SCI IO Port
unused SIOF Flame Sync / SCI Output Port
LB_SH_UART Receive Data (Network)
unused SIOF Receive Data / SCI INput Port
GND
EX_SH_UART Receive Data (external)
1.9V
unused
SH_SDA_Slot4 IIC Bus (Slot4)
SH_SCL_Slot4 IIC Bus (Slot4)
SH_SDA_Slot3 IIC Bus (Slot3)
GND
SH_SCL_Slot3 IIC Bus (Slot3)
3.3V
SH_SDA_3V IIC Bus
SH_SCL_3V IIC Bus
SH_SDA_Slot2 IIC Bus (Slot2)
SH_SCL_Slot2 IIC Bus (Slot2)
SH_SDA_Slot1 IIC Bus (Slot1)
SH_SCL_Slot2 IIC Bus (Slot2)
SH_SDA_S3V IIC Bus (Slot2)
SH_SCL_Slot2 IIC Bus (Slot2)
PW_SH_0 PW --> SH Input signal
UCLK USB Clock (48MHz)
- 138 -
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Always : L O / I / O
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"L" : Non Clear I
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"H" : ON O
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O
I / O
19200bps / 9600bps O
IO / IO
O / O
I / IO
19200bps / 9600bps O
IO / IO
IO / IO
19200bps / 9600bps I
I / I
19200bps / 9600bps I
I / I / I
"L" : Active IO
"L" : Active IO
"L" : Active IO
"L" : Active IO
"L" : Active IO
"L" : Active IO
"L" : Active IO
"L" : Active IO
"L" : Active IO
"L" : Active IO
"L" : Active IO
"L" : Active IO
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