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5.3
TCC1014 (VC2645QC)
1)
System Timing, Address Multiplex,
Device Select, MMU
By now,
it
should
be
apparent
that
controlling DRAMs
is a
fairly complex
task.
In
the
Color Computer
3,
it
is
done
by the
TCC1014
(VC2645QC: ACVC).
In
addition
to
address multiplexing,
RAS* and CAS* generation, WEO*, WEI*
timing control, and refresh
generation,
the
ACVC performs other
tasks.
It
contains
the
Master
Oscillator,
the
frequency
of
which
is
controlled
by
a
28.63636 MHz
(PAL:
28.4750 MHz) crystal
(XI). The
Master
Oscillator
is
divided
by eight to
give
a
3.579545 MHz color reference
signal
to
the
Video Display Generator
LOGIC and Composite Video Signal
(NTSC
version
only). This
reference
signal
is
then divided by 4
Cor
2)
again
to
provide
the
0.89 MHz
(1.78 MHz)
E
and Q clock signals
for
the
processor.
In
the
PAL version,
the
Master
Oscillator frequency
is
slightly
shifted down than
in the
NTSC version
for
fitting with
the
PAL encoder
circuit.
The
ACVC
(IC6)
also controls
access
to
the
memory, granting
access
to
the
processor during
the
high
time of
E
(CPU portion) and
access
to
the
VDG LOGIC during
the
low time of E (Video portion).
During
each access, whether
by the CPU or
the Video, the
ACVC must provide
appropriately synchronized RAS* and
CAS* signals,
as
well
as the
corresponding address signals,
to the
DRAMs. Note that the
DRAM
access time
must be twice
as
fast
as that
required
by the
CPU alone
in
order
to
be able to
respond
to
VDG accesses.
In
order
for the
ACVC chip
to
provide
the
appropriate addresses
to
the
DRAMs,
all
16
CPU address
lines are
input
to the
ACVC.
It
then
multiplexes
these into low order and
high order addresses
(ZO
through
Z8,
refer
to
MMU) which are sent
to the
DRAMs along with RAS* and
CAS*.
Another function
of this section
is
to
provide address decoding and
device selection
for the
computer.
Figure
5-6
shows how the
SO, SI,
and
S2
lines are connected
to IC9,
a
74LS138,
in
order
to
provide
appropriate signals
to
enable ROM
selection, PIA selection, and various
cartridge selection signals.
Due to
the
nature
of the ROMs and
in
order
to
prevent data bus contention,
the
ROMs are enabled only during
the
E
portion
of
a
read cycle.
+5V
R11
SLENB*>
IC
6
TCC1014
(VC2645QC)
SO
SI
S2
31
30
29
rn
Gl
G2A
G2B
A
B
C
YO
II
Y2
Y3
Y4
Y5
Y6
Y7
ROM*
CTS*
PIA*
N.C
N.C
N.C
—
SCS*(CARTRIDGE
1/0}
N.C
IC9
74LS138
Fig
5-6.
Color Computer
3
Address Decoding
-36-
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