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The CPU contains
a
number
of
inputs
which serve
to
initiate specific
sequences
of
events. The ones used by
the
Color Computer
3
are:
RESET*
—
Used on power up and
to
reinitialize
the CPU.
HALT*
-
Stops
the
program flow
after
the
completion
of
current instruction.
Execution will continue
after HALT
is
removed.
NMI*
-
Non-Maskable Interrupt
always causes
the
CPU
to
"interrupt"
its
normal
program
flow and execute
a
special "interrupt handler"
routine.
IRQ*
-
Interrupt Request. Similar
to
NMI but may be masked
(defeated) by setting
the
I
bit
in
the CC
register.
FIRQ*
-
Fast Interrupt Request.
Similar
to IRQ,
but
masked
by
the F bit.
It is
faster
because
it
doesn't preserve
all
registers
Cas do the
other interrupts).
Upon receipt
of the
RESET
signal, or
any of
the
interrupts
(if
enabled),
the CPU
will get
the
appropriate
subroutine address from
the
Vector
Table
(see the
memory map
in
Section
I,
System Description)
.
For
the
interrupt routines, registers are
preserved on
the
Stack
to be
restored
upon receipt
of the
RTI
(Return-from-Interrupt) instruction.
Other control lines used
in the
Color
Computer
3
are TSC
(Three-State
Control) and
the
R/W* (Read/Write*)
line.
The TSC line
is
an input
intended
for use
in
multiprocessor
or
DMA environment
and will cause
the
address and data lines
to go
into
a
three-state condition
if
high. Since
the
Color Computer
3
does not require
multiprocessing,
this line
is
permanently grounded. The R/W*
line
is
an output used by the
CPU
to
inform the external memory and
devices whether
the
data transfer
is
from the CPU
(a
write) or
to the
CPU
(a
read). Standard 68B09E Read/Write
timing
is
shown
in
Figure
5-3.
However,
in the
Color Computer
3,
this
timing
is
modified
by
the
ACVC
chip
so that the
addresses are
available
to
the
memory only during
the
active
E
time. This
presents
no
problem
as
long
as the
memory
is
sufficiently
fast.
-32-
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