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SAM CONTROL REGISTERS
Clear
Set
FFCO
-
FFC1
VO
FFC2
-
FFC3
VI
FFC4
-
FFC5
V2
FFC6
-
FFC7
FO
FFC8
-
FFC9
Fl
FFCA
-
FFCB
F2
FFCC
-
FFCD
F3
FFCE
-
FFCF
F4
FFDO
-
FFD1
F5
FFD2
-
FFD3
F6
FFD8
-
FFD9
Rl
FFDE
-
FFDF
TY
(FFCO
-
FFDF)
CoCo graphics mode select
CoCo graphics mode select
CoCo graphics mode select
CoCo Vertical offset
CoCo Vertical offset
CoCo Vertical offset
CoCo Vertical offset
CoCo Vertical offset
CoCo Vertical offset
CoCo Vertical offset
MPU Speed
ROM disable
NOTE: These bits
work
like the ones
in
the
Motorola SAM chip
(MC6883/SN74LS785)
in that
by writing
to the
upper address
of each
two-address
group (data
is
don't care), the bit
is
set; by
writing
to the
lower address,
the bit
is
cleared. The graphics modes and vertical offset bits are valid only
in
the
CoCo mode, but
the
other
two
bits are valid anytime. Note
the
only
semigraphics mode supported
is
Semi Four.
FFDF
FFDE
FFD9
FFD8
FFD3
FFD2
FFD1
FFD0
FFCF
FFCE
FFCD
FFCC
FFCB
FFCA
FFC9
FFC8
FFC7
FFC6
FFC5
FFC4
FFC3
FFC2
FFC1
FFCO
TY
Rl
F6
F5
F4
F3
F2
F1
F0
V2
VI
Vfl
MAP
TYPE
CPU
RATE
DISPLAY
OFFSET
(BINARY)
0.89MHz
-1.78MHz
DISPLAY
MODE
CONTROL
(SAM)
J
Address
of
Upper-
Left-
Most
Display
Element
=
9999 +
(1/2K
Offset)
N.U.
-,
r
RG6,
CG6
RG3
I-CG3
1
9
1
t-RG2
r-CG2
I-CG1.RG1
r-AI,
AE,
S4,
1
9
(S=Set
Bit,
C=Clear
Bit, all
Bits are cleared when SAM
is
reset)
Figure
1-3.
Memory Map
for
SAM Control Register
-21-
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