Chip Control Registers; Color Computer - Tandy 26-3334 Service Manual

1.5
Chip Control Registers
FF90
-
FFDF ACVC
IC6
FF90: Initialization Register (INITO)
BIT
7
=
COCO
BIT
6
=
M/P
BIT
5
=
IEN
BIT
4 =
FEN
BIT
3
=
MC3
BIT
2
=
MC2
BIT
1
=
MCI
BIT
=
MCO
=
Color Computer
1
and
2
Compatible
=
MMU enabled
=
Chip IRQ output enabled
=
Chip FIRQ output enabled
= DRAM
at
XFEXX
is
constant
=
Standard
SCS
ROM map control (See table below)
ROM map control (See table below)
MCI MCO ROM mapping
1
1
X
1
16K Internal,
16K External
32K Internal
32K External (except
for vectors)
FF91: Initialization Register
1
(INIT1)
BIT
7
BIT
6
BIT
5
=
TINS
Timer Input
Select:
1
=
70
nsec
/
BIT
4
BIT
3
BIT
2
BIT
1
BIT
=
TR MMU Task Register Select
63 psec
FF92:
FF93:
Interrupt Request Enable Register (IRQENR)
Interrupt from Timer enabled
Horizontal Border IRQ enabled
Vertical Border IRQ enabled
Serial Data IRQ enabled
Keyboard
IRQ enabled
Cartridge
IRQ
enabled
Fast Interrupt Request Enable Register (FIRQENR)
Interrupt
from Timer enabled
Horizontal Border FIRQ enabled
Vertical Border FIRQ enabled
Serial Data FIRQ enabled
Keyboard FIRQ enabled
Cartridge FIRQ enabled
BIT
7
-
BIT
6
-
BIT
5
=
TMR
BIT
4
=
HBORD
BIT
3
=
VBORD
BIT
2
=
EI2
BIT
1
=
Ell
BIT
=
EIO
Fast
Int
BIT
7
-
BIT
6
-
BIT
5 =
TMR
BIT
4
=
HBORD
BIT
3
=
VBORD
BIT
2
=
EI2
BIT
1
=
Ell
BIT
=
EIO
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