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CP2120 E
V A L U A T I O N
1. Kit Contents
The CP2120 Evaluation Kit contains a CP2120 evaluation board and a power supply. The following supporting
documents can be downloaded from www.silabs.com:
CP2120 Data Sheet
AN311: CP2120 Porting Guide
2. CP2120 Hardware Interface
The evaluation board is connected to a SPI master and to SMBus devices as shown in Figure 1.
1. Connect the SPI Master's SPI bus lines to the CP2120. If The CP2120 is the only SPI slave device on the
SPI bus, then the CS pin can be tied low.
2. Connect the CP2120's INT pin to a port pin of the SPI Master.
3. Connect the CP2120 to SMBus devices through the SMBus lines.
Please refer to "4. Evaluation Board" on page 2 for more information about these steps.
SPI Master
3. CP2120 Operation
Once connected as shown in Figure 1, the SPI Master issues commands to the CP2120 across the SPI bus. The
CP2120 responds to commands by initiating an SMBus transfer with SMBus slave devices, reading from or writing
to internal registers, or interfacing with general purpose input/output (I/O) port pins. When an SMBus transaction
completes, the CP2120 pulls the INT pin low, which signals the SPI Master that the command has been processed.
Rev. 0.1 9/06
K
U
I T
S E R
SPI Bus
MOSI
SCK
CS
CP2120
MISO
INT
Figure 1. System Connections
Copyright © 2006 by Silicon Laboratories
C P 2 1 2 0 - E K
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G
S
U I D E
SMBus
SDA
SCL
SMBus
Device
SMBus
Device
SMBus
Device
CP2120-EK
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Summary of Contents for Silicon Laboratories CP2120
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Page 1: Kit Contents
The evaluation board is connected to a SPI master and to SMBus devices as shown in Figure 1. 1. Connect the SPI Master’s SPI bus lines to the CP2120. If The CP2120 is the only SPI slave device on the SPI bus, then the CS pin can be tied low. -
Page 2: Evaluation Board
CP2120-EK 4. Evaluation Board The CP2120 evaluation board comes with a CP2120 device pre-installed for system evaluation and development. Numerous I/O connections are provided to facilitate prototyping using the evaluation board. Refer to Figure 2 for the locations of the various I/O connectors. - Page 3 CP2120-EK 4.1. J2—SPI Master Interface Connector J2 provides the SPI Master access to the CP2120 SPI, control, and reset lines. Table 1 shows the pinout of the J2 header. Table 1. Pinout for J2 Pin 1 SPI Bus—SCLK Pin 2 SPI Bus—MISO...
- Page 4 Note: When operating the SPI bus with a header on J4, only drive the MOSI pin whenever data is being transmitted to the CP2120. When the SPI bus is idle, or when the CP2120 is transmitting data, the SPI master must set its MOSI pin into an open-drain state to avoid port pin contention.
- Page 5 CP2120-EK 4.6. J10—General Purpose I/O Interface Connector J10 enables off-board access to the CP2120’s eight general purpose I/O pins, as well as the Edge- Triggered Interrupt Source pin. Table 3 shows the pinout for this header. Table 3. Pinout for J10...
- Page 6 CP2120-EK 5. Schematic Rev. 0.1...
- Page 7 CP2120-EK OTES Rev. 0.1...
- Page 8 Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per- sonal injury or death may occur.
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