Sailor RE2100 Technical Manual page 114

5 CIRCUIT DESCRIPTION AND SCHEMATIC DIAGRAMS RE2100
PASSIVE LOOP FILTER
The components R28, R31, C11, C51, C54, and L22 constitute a chebychev lowpass filter with cut-off
frequency equal to approximately 10 kHz.
The major task of the passive filter is to prevent spurious signals arised from the phase detector and
divider circuit, to modulate the VCO and generate sidebands to the VCO output signal.
ACTIVE LOOP FILTER
The filter consists of U16, C66, R33, and R38. The filter secures stabilization in the loop system and is
of vital importance in determination of the loop system bandwidth
PHASE DETECTOR
The phase detector is of the sample and hold type. The detector consists of a sequential phase detector
followed by the current switch, the ramp generator and the sample and hold circuit.
U26 together with U27 form the sequential phase detector which converts the phase difference between
the reference signal and the signal from the programmable divider to a square wave signal measurable
on U26 pin 6. The duty cycle of the square wave signal is inverse proportional to the phase difference.
The sequential phase detector controls the current switch, which is built-up around Q25, D17, R93, D16,
and D15. When the signal on basis of Q25 is at high state, D16 is switched on, the potential on the cathode
of D15 is increased, and D15 is switched off.
When the signal on basis of Q25 is at low state, D16 is switched off, the potential on the cathode of D15
is decreased, and D15 is switched on. The amount of current flowing through D15 and D16 respectively
is determined by the current mirror circuit described elsewhere.
The ramp generator, built-up around U21 and C112, integrates the current drawn from U21 pin 2 in regard
to time. The ramp generator output voltage is then linear in regard to the size of current flowing through
the switch diode D15 and the period of time the diode is switched on.
Q24 connected in parallel to C112 constitutes a switch, which resets the ramp generator by discharging
C112.
The switch is open when the gate voltage is at low state and vice versa.
The ramp generator and current switch connected with the sequential phase detector imply a phase
detector where the output voltage, in a certain period of time in every reference cycle, is linear in regard
to the phase difference between the reference signal and the signal from the programmable divider. In
this period the output voltage has to be sampled and held and this is done by the sample & hold circuit,
consisting of U19, R64, C95, Q19, and R77.
Q19 functions as the switch, which carries out the sampling. The switch is open when the gate voltage
is at low state and vice versa.
C95 is charged to the phase detector voltage through R77 when the sample switch is closed, and carries
out the hold function when the sample switch is open.
The voltage on C95 is led to the active loop filter through the voltage follower U19.
CURRENT MIRROR
The current mirror is built-up around transistor array U20 and the circuit generates reference circuit for
the phase detector and the API-circuit.
The current mirror is so designed that the ratio between reference current for phase detector and API-
circuit respectively will be kept as a constant regardless of the temperature. A change in one of the
currents will be reflected or mirrored into the other.
The nominal value of reference current for the API circuit can be adjusted by means of potentiometer R88.
CONTROL SIGNAL LOGIC
The circuit is built-up around one 8-bit counter U32, which is clocked by the input signal to the reference
divider. The clock frequency is 5.36576 MHz.
The counter is reset by the output signal from the reference divider.
The control logic delivers reset signal to the ramp generator and sample signal for the sample & hold
circuit. The output signals from the circuit are generated through detection of which state the 8-bit counter
is in, and the detection is done by means of the logical circuitry formed by U25 and U29.
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