Receiver Unit (Module 1) Part No. 625631; Circuit Description And Schematic Diagrams 5.1 Receiver Unit (Module 1) Part No. 625631 - Sailor RE2100 Technical Manual

RE2100
5 CIRCUIT DESCRIPTION AND SCHEMATIC DIAGRAMS

5.1 RECEIVER UNIT (MODULE 1) PART NO. 625631

The receiver unit consists of a 70.0 MHz to 10.7 MHz mixer followed by an SSB/AM filter and a gain
regulated IF amplifier. From the amplifier the signal is fed to the detector and low frequency filter unit. The
receiver unit contains low frequency derived squelchs which can be set to control the low frequency
output.
SECOND MIXER AND CRYSTAL FILTERS
The signal from the 70 MHz selectivity (module 2) is led through the balanced transformer TR01 to the
gates of the J-FET's Q01 and Q02.
The second LO signal from the frequency synthesizer (module 3) is led through the LO-buffer Q03 and
BPF (L01, L03, L04, and C04, C05, C11) in order to give about +17 dBm signal to the sources of the FET's.
The mixed signals are fed through the balanced transformer TR02 and the impedance matching network
(C17-C19 and R10) to one of the two high order monolitic crystal filters FL01 or FL02. The filter selection
is controlled by the microprocessor through the shift register U10, pin 2.
IF AMPLIFIER
The signal from the crystal filters is fed through the diode D07 or D08 to the IF amplifier.
The IF amplifier consists of transistors Q07-Q11 and filter FL03 in cascade.
The gain in Q07, Q08, and Q09, which are dual gate Mos-FET's, is controlled by the AGC voltage applied
to gate 2 of the FET's. This is done to keep the input level to the detector at the same level, independent
of the input level to the receiver. From Q09 the signal is led to an amplifier built-up around Q10 and further
to the ceramic filter FL03, which reduces the noise bandwidth to about 300 kHz. From the ceramic filter,
the signal is fed through the emitter follower Q11 to the detector.
AGC GENERATOR
From the amplifier Q11 the signal is fed to the common emitter amplifier Q16. The voltage gain in this
amplifier determines through the AGC system the magnitude of the output from the IF amplifier.
From the amplifier Q16 the signal is fed to transistor Q14, which together with R89, R91, C72, and C71
forms a magnitude detector.
SSB MODE
In SSB mode the signal from the magnitude detector ensures fast control of the gain in the IF amplifier.
A slow control of the gain in the IF amplifier is activated by feeding the detector output voltage to the
amplifier U03/2. U03/2 buffers the charging of C69 through D11 and R69 and the charging is removed
from C69 through R63.
The voltage on C69 is fed through the unity gain buffer U03/1 and D10 to the cathode of D14, where it
is added to the actual voltage level from the detector. The added voltage is then subtracted from a
reference voltage in U03/3 to make the AGC voltage, which is fed through an LP filter to the gates of Q07,
Q08, and Q09.
The fast AGC system ensures noise immunity and the slow AGC system will decrease distortion caused
by the AGC on an SSB signal.
AM MODE
In AM mode C71 is connected parallel to C72 through Q15. This increases both rise and fall time for the
(fast) AGC system, so that modulation compression does not occur. The slow SSB-AGC is disabled by
shunting C69 through Q04.
The manual IF gain voltage is added to the AGC system through D13. In scan mode the IF gain is set to
max., independent of the position of the IF gain potentiometer (on module 7), by short-circuiting the
potentiometer with Q12.
To switch the AGC system off, C71 (and C72 in AM mode) is short-circuited with Q13.
All mode shifts in the AGC system are controlled by the microprocessor through the shift register U10.
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